diff options
| author | Francesco Dolcini <francesco.dolcini@toradex.com> | 2023-12-11 17:51:46 +0100 |
|---|---|---|
| committer | Francesco Dolcini <francesco.dolcini@toradex.com> | 2023-12-11 17:51:46 +0100 |
| commit | 4922f58b8c4e55fc844b65513131032aacdc1b0e (patch) | |
| tree | 0207f9602f784c4ad76729d6e4f727dc27c3fb3b /drivers | |
| parent | 89290c06f01e507f5da8edd3afe90a81888fddfa (diff) | |
| parent | b0d717b732ee28e446baf94522b3491e590f7fbb (diff) | |
Merge tag '09.01.00.008' into toradex_ti-u-boot-2023.04-09.01.00.008
RC Release 09.01.00.008
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/misc/k3_avs.c | 22 | ||||
| -rw-r--r-- | drivers/ram/k3-ddrss/k3-ddrss.c | 11 |
2 files changed, 26 insertions, 7 deletions
diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index dbf79040e0..38411e79c8 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -473,6 +473,27 @@ static struct vd_data j721e_vd_data[] = { { .id = -1 }, }; +static struct vd_data j721s2_vd_data[] = { + { + .id = J721E_VDD_MPU, + .opp = AM6_OPP_NOM, + .dev_id = 202, /* J721S2_DEV_A72SS0_CORE0 */ + .clk_id = 0, /* ARM clock */ + .opps = { + [AM6_OPP_NOM] = { + .volt = 880000, /* TBD in DM */ + .freq = 2000000000, + }, + }, + }, + { .id = -1 }, +}; + +static struct vd_config j721s2_vd_config = { + .efuse_xlate = am6_efuse_xlate, + .vds = j721s2_vd_data, +}; + static struct vd_config j721e_vd_config = { .efuse_xlate = am6_efuse_xlate, .vds = j721e_vd_data, @@ -486,6 +507,7 @@ static struct vd_config am654_vd_config = { static const struct udevice_id k3_avs_ids[] = { { .compatible = "ti,am654-avs", .data = (ulong)&am654_vd_config }, { .compatible = "ti,j721e-avs", .data = (ulong)&j721e_vd_config }, + { .compatible = "ti,j721s2-avs", .data = (ulong)&j721s2_vd_config }, {} }; diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 75d13df8ad..28129d52a6 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -138,6 +138,7 @@ struct k3_ddrss_desc { u32 ddr_freq1; u32 ddr_freq2; u32 ddr_fhs_cnt; + u32 dram_class; struct udevice *vtt_supply; u32 instance; lpddr4_obj *driverdt; @@ -243,14 +244,11 @@ static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss) static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd) { - u32 dram_class; struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance; debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n"); - dram_class = k3_lpddr4_read_ddr_type(pd); - - switch (dram_class) { + switch (ddrss->dram_class) { case DENALI_CTL_0_DRAM_CLASS_DDR4: break; case DENALI_CTL_0_DRAM_CLASS_LPDDR4: @@ -263,13 +261,12 @@ static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd) static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss) { - u32 dram_class; int ret; lpddr4_privatedata *pd = &ddrss->pd; - dram_class = k3_lpddr4_read_ddr_type(pd); + ddrss->dram_class = k3_lpddr4_read_ddr_type(pd); - switch (dram_class) { + switch (ddrss->dram_class) { case DENALI_CTL_0_DRAM_CLASS_DDR4: /* Set to ddr_freq1 from DT for DDR4 */ ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); |