clk: clk-k3: Reduce the parent clock configuration threshold to 1/8

After performing DFS on A72, the clk-k3 driver causes the reboot to fail
due to fault clock re-initialization

The clk-k3.c driver performs PLL setup based on the difference between
the requested clock rate and current clock rate. If the difference is
found to be more that 50%, in that case it recurses to the clock's parent
for changing its frequency and setting up the PLL. If the difference is
found to be less than that, it assumes that it is a rounding error in the
divider and tries to accommodate for that without touching the parent
clocks.

So, 5% to 50% difference, it assumes it to be a rounding error. From 50%
difference onward it treats it as a HSDIV+PLL configuration case and
sets everything correctly.

So when a fresh boot happens, the A72 clock frequency is found to be at
19.2MHz, which is way less than 2GHz and hence it crosses 50% barrier and
gets properly setup. But when we change the A72 frequency to 1.5 GHz
through DFS, the difference is only of 25% (<50%). So, when we do a
reboot, it doesn't configure the parent clocks and PLLs, it just tries to
make the value close to 2GHz, but that doesn't work.

So, reduce the threshold from 50% to 12.5%, to reconfigure the clocks
correctly at reboot, allowing to boot up after a DFS operation.

Signed-off-by: Apurva Nandan <a-nandan@ti.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/clk/clk-k3.c b/drivers/clk/clk-k3.c
index fd6e779399..ea6fe762d3 100644
--- a/drivers/clk/clk-k3.c
+++ b/drivers/clk/clk-k3.c
@@ -281,7 +281,7 @@ static ulong ti_clk_set_rate(struct clk *clk, ulong rate)
 	 * following directly a PLL
 	 */
 
-	if (diff > rate / div / 2) {
+	if (diff > rate / div / 8) {
 		ulong pll_tgt;
 		int pll_div = 0;