diff options
| author | Vignesh Raghavendra <vigneshr@ti.com> | 2023-01-17 20:22:30 +0530 |
|---|---|---|
| committer | Anand Gadiyar <gadiyar@ti.com> | 2023-01-18 18:29:35 -0600 |
| commit | f8cb8ab8a3e9fbb67bf599d4b95537fe84b2b22e (patch) | |
| tree | e3bcde517a9f64dca5caa3fb0e25496ff66fa18f /drivers | |
| parent | 058469c6a8b3e35316a6349f339a328ae414d4c5 (diff) | |
clk: clk-k3: Fix possible failure wrt PLL reconfig
Check if the parent pll rate is indeed set to target rate, if not
fallback adjusting dividers to get within 5% of requested rate
This is required to set correct rate for DDR PLLs on AM62A resulting in
lower DDR bandwidth when measured with lmbench (bw_mem)
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/clk-k3.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/clk/clk-k3.c b/drivers/clk/clk-k3.c index 844accb796..6c47f43786 100644 --- a/drivers/clk/clk-k3.c +++ b/drivers/clk/clk-k3.c @@ -244,7 +244,7 @@ static ulong ti_clk_set_rate(struct clk *clk, ulong rate) int div = 1; ulong child_rate; const struct clk_ops *ops; - ulong new_rate, rem; + ulong new_rate, rem, temp_rate; ulong diff, new_diff; /* @@ -287,7 +287,7 @@ static ulong ti_clk_set_rate(struct clk *clk, ulong rate) * following directly a PLL */ - if (diff > rate / div / 8) { + if ((diff > rate / div / 8) && clk_get_parent(clkp)) { ulong pll_tgt; int pll_div = 0; @@ -317,9 +317,11 @@ static ulong ti_clk_set_rate(struct clk *clk, ulong rate) debug("%s: pll_tgt=%u, rate=%u, div=%u\n", __func__, (u32)pll_tgt, (u32)rate, pll_div); - clk_set_rate(clkp, pll_tgt); + temp_rate = clk_set_rate(clkp, pll_tgt); + if (temp_rate == pll_tgt) + return clk_set_rate(clk, rate / div) * div; - return clk_set_rate(clk, rate / div) * div; + clkp = clk; } /* |