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authorTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>2018-05-14 19:38:13 +0300
committerTom Rini <trini@konsulko.com>2018-05-26 12:46:50 -0400
commitd71975ae6e0f3dc1c0c96d3a8cc0120a266305b9 (patch)
treea7684ddd6ff0eb0c17fa38ca840a2636342d54b0 /drivers
parented12a89d0738dd030c42a608efa7a72dd4a1f6da (diff)
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources
Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/pci_auto.c6
-rw-r--r--drivers/pci/pci_auto_common.c7
-rw-r--r--drivers/pci/pci_auto_old.c5
3 files changed, 13 insertions, 5 deletions
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index d1feb503a0..d7237f6eee 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -98,7 +98,8 @@ void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
}
if (!enum_only && pciauto_region_allocate(bar_res, bar_size,
- &bar_value) == 0) {
+ &bar_value,
+ found_mem64) == 0) {
/* Write it out and update our limit */
dm_pci_write_config32(dev, bar, (u32)bar_value);
@@ -140,7 +141,8 @@ void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
debug("PCI Autoconfig: ROM, size=%#x, ",
(unsigned int)bar_size);
if (pciauto_region_allocate(mem, bar_size,
- &bar_value) == 0) {
+ &bar_value,
+ false) == 0) {
dm_pci_write_config32(dev, rom_addr,
bar_value);
}
diff --git a/drivers/pci/pci_auto_common.c b/drivers/pci/pci_auto_common.c
index d90dbcf91a..183787333e 100644
--- a/drivers/pci/pci_auto_common.c
+++ b/drivers/pci/pci_auto_common.c
@@ -32,7 +32,7 @@ void pciauto_region_align(struct pci_region *res, pci_size_t size)
}
int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
- pci_addr_t *bar)
+ pci_addr_t *bar, bool supports_64bit)
{
pci_addr_t addr;
@@ -48,6 +48,11 @@ int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
goto error;
}
+ if (upper_32_bits(addr) && !supports_64bit) {
+ debug("Cannot assign 64-bit address to 32-bit-only resource\n");
+ goto error;
+ }
+
res->bus_lower = addr + size;
debug("address=0x%llx bus_lower=0x%llx\n", (unsigned long long)addr,
diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c
index bc119fba87..e705a3072e 100644
--- a/drivers/pci/pci_auto_old.c
+++ b/drivers/pci/pci_auto_old.c
@@ -108,7 +108,8 @@ void pciauto_setup_device(struct pci_controller *hose,
}
#ifndef CONFIG_PCI_ENUM_ONLY
- if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
+ if (pciauto_region_allocate(bar_res, bar_size,
+ &bar_value, found_mem64) == 0) {
/* Write it out and update our limit */
pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
@@ -150,7 +151,7 @@ void pciauto_setup_device(struct pci_controller *hose,
debug("PCI Autoconfig: ROM, size=%#x, ",
(unsigned int)bar_size);
if (pciauto_region_allocate(mem, bar_size,
- &bar_value) == 0) {
+ &bar_value, false) == 0) {
pci_hose_write_config_dword(hose, dev, rom_addr,
bar_value);
}