diff options
| author | Dhruva Gole <d-gole@ti.com> | 2022-11-18 17:40:00 +0530 |
|---|---|---|
| committer | Anand Gadiyar <gadiyar@ti.com> | 2022-11-21 09:33:40 -0600 |
| commit | af66450d92848384af1c76323f12865f87b7d336 (patch) | |
| tree | 6dc4bdd30298433d389d2c4b2ead87259a0ff8fb /drivers | |
| parent | bdd9c3bec0d5a6228839be23e4f23666356b43b8 (diff) | |
spi: cadence_qspi: setup ADDR Bits in cmd reads
Setup the Addr bit field while issuing register reads in STIG mode. This
is needed for example flashes like cypress define in their transaction
table that to read any register there is 1 cmd byte and a few more address
bytes trailing the cmd byte. Absence of addr bytes will obviously fail
to read correct data from flash register that maybe requested by flash
driver because the controller doesn't even specify which address of the
flash register the read is being requested from.
Also update some LSB macros to use BIT(n) macro instead for better
readability.
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 9e938a2fc3..86cd67ae9c 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -149,7 +149,7 @@ #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 -#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 +#define CQSPI_REG_CMDCTRL_ADDR_EN BIT(19) #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 @@ -744,6 +744,19 @@ int cadence_qspi_apb_command_read(struct cadence_spi_platdata *plat, /* 0 means 1 byte. */ reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); + + /* setup ADDR BIT field */ + if (op->addr.nbytes) { + writel(op->addr.val, plat->regbase + CQSPI_REG_CMDADDRESS); + /* + * address bytes are zero indexed + */ + reg |= (((op->addr.nbytes - 1) & + CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) << + CQSPI_REG_CMDCTRL_ADD_BYTES_LSB); + reg |= CQSPI_REG_CMDCTRL_ADDR_EN; + } + status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg); if (status != 0) return status; |