diff options
| author | Peng Fan <peng.fan@nxp.com> | 2019-12-30 09:58:52 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2020-01-08 13:20:08 +0100 |
| commit | 4a41a1a6f06ed86feae9f52d2e8ece5cce0a850d (patch) | |
| tree | 6d4396c6eee69cb7da478b63c81bdd4ce1a92c1f /drivers | |
| parent | 67f3f32c6a5a3e542ebccb624d683f0c04150b61 (diff) | |
ddr: imx8m: Add DRAM PLL to generate 1000Mhz output
We will generate DRAM 4000MT/s as default for i.MX8MP.
So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/imx/imx8m/ddrphy_utils.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c index 863fb43897..9ac7ca923c 100644 --- a/drivers/ddr/imx/imx8m/ddrphy_utils.c +++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c @@ -106,6 +106,10 @@ int wait_ddrphy_training_complete(void) void ddrphy_init_set_dfi_clk(unsigned int drate) { switch (drate) { + case 4000: + dram_pll_init(MHZ(1000)); + dram_disable_bypass(); + break; case 3200: dram_pll_init(MHZ(800)); dram_disable_bypass(); |