diff options
| author | Ye Li <ye.li@nxp.com> | 2019-05-08 00:09:54 -0700 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2019-05-29 20:02:04 -0700 |
| commit | 6d6b0c810cdc7f5b60d2959d9b5cd891bc5b8296 (patch) | |
| tree | 9c734bd071d8cc922c12c7263fa6deb30cc6d09d /drivers | |
| parent | d74caad677814a0366cb1220d1b998de3cb01588 (diff) | |
MLK-21889-6 video: Add iMX8M Nano support to MIPI DSI
Add the IMX8MN to the SEC MIPI DSI kconfig dependency, and
update display GPR registers for iMX8MN changes.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/video/Kconfig | 4 | ||||
| -rw-r--r-- | drivers/video/mxsfb.c | 7 | ||||
| -rw-r--r-- | drivers/video/sec_mipi_dsim.c | 16 |
3 files changed, 21 insertions, 6 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 57d21d625a..6491648b3c 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -560,9 +560,9 @@ config IMX_SEC_MIPI_DSI bool "i.MX Samsung's MIPI DSI" default n select IMX_MIPI_DSI_BRIDGE - depends on VIDEO && (IMX8MM || MX7) + depends on VIDEO && (IMX8MM || IMX8MN || MX7) help - Support for i.MX7 and i.MX8MM MIPI DSI controller. + Support for i.MX7, i.MX8MM and i.MX8MN MIPI DSI controller. config MXC_EPDC bool "i.MX EPDC support" diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 838c037e5b..f3f31f796b 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -299,8 +299,13 @@ void *video_hw_init(void) printf("%s\n", panel.modeIdent); #ifdef CONFIG_IMX_MIPI_DSI_BRIDGE + int dsi_ret; imx_mipi_dsi_bridge_mode_set(&fbmode); - imx_mipi_dsi_bridge_enable(); + dsi_ret = imx_mipi_dsi_bridge_enable(); + if (dsi_ret) { + printf("Enable DSI bridge failed, err %d\n", dsi_ret); + return NULL; + } #endif /* Start framebuffer */ diff --git a/drivers/video/sec_mipi_dsim.c b/drivers/video/sec_mipi_dsim.c index 7329d23dbf..a56414f0cb 100644 --- a/drivers/video/sec_mipi_dsim.c +++ b/drivers/video/sec_mipi_dsim.c @@ -207,10 +207,20 @@ /* Dispmix Control & GPR Registers */ #define DISPLAY_MIX_SFT_RSTN_CSR 0x00 +#ifdef CONFIG_IMX8MN +#define MIPI_DSI_I_PRESETn_SFT_EN BIT(0) | BIT(1) +#else #define MIPI_DSI_I_PRESETn_SFT_EN BIT(5) +#endif #define DISPLAY_MIX_CLK_EN_CSR 0x04 + +#ifdef CONFIG_IMX8MN +#define MIPI_DSI_PCLK_SFT_EN BIT(0) +#define MIPI_DSI_CLKREF_SFT_EN BIT(1) +#else #define MIPI_DSI_PCLK_SFT_EN BIT(8) #define MIPI_DSI_CLKREF_SFT_EN BIT(9) +#endif #define GPR_MIPI_RESET_DIV 0x08 /* Clock & Data lanes reset: Active Low */ #define GPR_MIPI_S_RESETN BIT(16) @@ -273,10 +283,10 @@ static void disp_mix_dsim_lanes_reset(struct sec_mipi_dsim *dsim, bool reset) { if (!reset) /* release lanes reset */ - setbits_le32(dsim->disp_mix_gpr_base + GPR_MIPI_RESET_DIV, GPR_MIPI_S_RESETN | GPR_MIPI_M_RESETN); + setbits_le32(dsim->disp_mix_gpr_base + GPR_MIPI_RESET_DIV, GPR_MIPI_M_RESETN); else /* reset lanes */ - clrbits_le32(dsim->disp_mix_gpr_base + GPR_MIPI_RESET_DIV, GPR_MIPI_S_RESETN | GPR_MIPI_M_RESETN); + clrbits_le32(dsim->disp_mix_gpr_base + GPR_MIPI_RESET_DIV, GPR_MIPI_M_RESETN); } static void sec_mipi_dsim_wr_tx_header(struct sec_mipi_dsim *dsim, @@ -729,7 +739,7 @@ static int sec_mipi_dsim_bridge_enable(struct mipi_dsi_bridge_driver *bridge_dri ret = sec_mipi_dsim_config_pll(dsim_host); if (ret) { printf("dsim pll config failed: %d\n", ret); - return -EPERM; + return ret; } /* config dphy timings */ |