ENGR00181337-2 i.mx6 : i.mx6sl arm2 add EPDC support

Add EPDC splash screen support for U-Boot

Signed-off-by: Danny Nold <dannynold@freescale.com>

2 files changed, 208 insertions, 40 deletions

diff --git a/drivers/video/mxc_epdc_fb.c b/drivers/video/mxc_epdc_fb.c
index 6430cc95d07..6dfa1a40766 100644
--- a/drivers/video/mxc_epdc_fb.c
+++ b/drivers/video/mxc_epdc_fb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -26,7 +26,6 @@
 #include <linux/list.h>
 #include <linux/err.h>
 #include <linux/types.h>
-#include <asm/arch/mx50.h>
 
 #include "mxc_epdc_fb.h"
 
@@ -47,6 +46,8 @@ int lcd_color_bg;
 short console_col;
 short console_row;
 
+int rev;
+
 void lcd_initcolregs(void)
 {
 }
@@ -160,6 +161,7 @@ static void epdc_set_vertical_timing(u32 vert_start, u32 vert_end,
 static void epdc_init_settings(void)
 {
 	u32 reg_val;
+	int num_ce;
 
 	/* EPDC_CTRL */
 	reg_val = REG_RD(EPDC_BASE, EPDC_CTRL);
@@ -205,8 +207,9 @@ static void epdc_init_settings(void)
 	 * PIXELS_PER_SDCLK = 4
 	 */
 	reg_val =
-		((4 << EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET) &
-		EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK)
+		((panel_info.epdc_data.epdc_timings.vscan_holdoff <<
+			EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET) &
+			EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK)
 		| EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4;
 	REG_WR(EPDC_BASE, EPDC_TCE_CTRL, reg_val);
 
@@ -223,14 +226,18 @@ static void epdc_init_settings(void)
 
 	/* EPDC_TCE_OE */
 	reg_val =
-		((10 << EPDC_TCE_OE_SDOED_WIDTH_OFFSET) &
-		EPDC_TCE_OE_SDOED_WIDTH_MASK)
-		| ((20 << EPDC_TCE_OE_SDOED_DLY_OFFSET) &
-		EPDC_TCE_OE_SDOED_DLY_MASK)
-		| ((10 << EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET) &
-		EPDC_TCE_OE_SDOEZ_WIDTH_MASK)
-		| ((20 << EPDC_TCE_OE_SDOEZ_DLY_OFFSET) &
-		EPDC_TCE_OE_SDOEZ_DLY_MASK);
+		((panel_info.epdc_data.epdc_timings.sdoed_width <<
+			EPDC_TCE_OE_SDOED_WIDTH_OFFSET) &
+			EPDC_TCE_OE_SDOED_WIDTH_MASK)
+		| ((panel_info.epdc_data.epdc_timings.sdoed_delay <<
+			EPDC_TCE_OE_SDOED_DLY_OFFSET) &
+			EPDC_TCE_OE_SDOED_DLY_MASK)
+		| ((panel_info.epdc_data.epdc_timings.sdoez_width <<
+			EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET) &
+			EPDC_TCE_OE_SDOEZ_WIDTH_MASK)
+		| ((panel_info.epdc_data.epdc_timings.sdoez_delay <<
+			EPDC_TCE_OE_SDOEZ_DLY_OFFSET) &
+			EPDC_TCE_OE_SDOEZ_DLY_MASK);
 	REG_WR(EPDC_BASE, EPDC_TCE_OE, reg_val);
 
 	/* EPDC_TCE_TIMING1 */
@@ -238,18 +245,22 @@ static void epdc_init_settings(void)
 
 	/* EPDC_TCE_TIMING2 */
 	reg_val =
-		((480 << EPDC_TCE_TIMING2_GDCLK_HP_OFFSET) &
-		EPDC_TCE_TIMING2_GDCLK_HP_MASK)
-		| ((20 << EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET) &
-		EPDC_TCE_TIMING2_GDSP_OFFSET_MASK);
+		((panel_info.epdc_data.epdc_timings.gdclk_hp_offs <<
+			EPDC_TCE_TIMING2_GDCLK_HP_OFFSET) &
+			EPDC_TCE_TIMING2_GDCLK_HP_MASK)
+		| ((panel_info.epdc_data.epdc_timings.gdsp_offs <<
+			EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET) &
+			EPDC_TCE_TIMING2_GDSP_OFFSET_MASK);
 	REG_WR(EPDC_BASE, EPDC_TCE_TIMING2, reg_val);
 
 	/* EPDC_TCE_TIMING3 */
 	reg_val =
-		((0 << EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET) &
-		EPDC_TCE_TIMING3_GDOE_OFFSET_MASK)
-		| ((1 << EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET) &
-		EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK);
+		((panel_info.epdc_data.epdc_timings.gdoe_offs <<
+			EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET) &
+			EPDC_TCE_TIMING3_GDOE_OFFSET_MASK)
+		| ((panel_info.epdc_data.epdc_timings.gdclk_offs <<
+			EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET) &
+			EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK);
 	REG_WR(EPDC_BASE, EPDC_TCE_TIMING3, reg_val);
 
 	/*
@@ -261,8 +272,11 @@ static void epdc_init_settings(void)
 	 * SDDO_INVERT = DISABLED
 	 * PIXELS_PER_CE = display horizontal resolution
 	 */
+	num_ce = panel_info.epdc_data.epdc_timings.num_ce;
+	if (num_ce == 0)
+		num_ce = 1;
 	reg_val = EPDC_TCE_SDCFG_SDCLK_HOLD | EPDC_TCE_SDCFG_SDSHR
-		| ((1 << EPDC_TCE_SDCFG_NUM_CE_OFFSET) & EPDC_TCE_SDCFG_NUM_CE_MASK)
+		| ((num_ce << EPDC_TCE_SDCFG_NUM_CE_OFFSET) & EPDC_TCE_SDCFG_NUM_CE_MASK)
 		| EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS
 		| ((panel_info.vl_col << EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET) &
 		EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK);
@@ -350,7 +364,6 @@ static void draw_splash_screen(void)
 		msleep(100);
 	}
 	debug("Splash screen update failed!\n");
-
 }
 
 void lcd_enable(void)
@@ -391,6 +404,8 @@ void lcd_panel_disable(void)
 
 void lcd_ctrl_init(void *lcdbase)
 {
+	unsigned int val;
+
 	/*
 	 * We rely on lcdbase being a physical address, i.e., either MMU off,
 	 * or 1-to-1 mapping. Might want to add some virt2phys here.
@@ -416,11 +431,20 @@ void lcd_ctrl_init(void *lcdbase)
 	debug("resolution %dx%d, bpp %d\n", (int)panel_info.vl_col,
 		(int)panel_info.vl_row, NBITS(panel_info.vl_bpix));
 
+	/* Get EPDC version */
+	val = REG_RD(EPDC_BASE, EPDC_VERSION);
+	rev = ((val & EPDC_VERSION_MAJOR_MASK) >>
+				EPDC_VERSION_MAJOR_OFFSET) * 10
+			+ ((val & EPDC_VERSION_MINOR_MASK) >>
+				EPDC_VERSION_MINOR_OFFSET);
+
 	/* Set framebuffer pointer */
 	REG_WR(EPDC_BASE, EPDC_UPD_ADDR, (u32)lcdbase);
 
 	/* Set Working Buffer pointer */
 	REG_WR(EPDC_BASE, EPDC_WB_ADDR, panel_info.epdc_data.working_buf_addr);
+	if (rev > 20)
+		REG_WR(EPDC_BASE, EPDC_WB_ADDR_TCE, panel_info.epdc_data.working_buf_addr);
 
 	/* Get waveform data address and offset */
 	if (setup_waveform_file()) {
diff --git a/drivers/video/mxc_epdc_fb.h b/drivers/video/mxc_epdc_fb.h
index e078538bd5d..30012aceea6 100644
--- a/drivers/video/mxc_epdc_fb.h
+++ b/drivers/video/mxc_epdc_fb.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -43,11 +43,13 @@
 #define EPDC_FIFOCTRL_CLR		(0x0a8)
 #define EPDC_FIFOCTRL_TOG		(0x0ac)
 #define EPDC_UPD_ADDR			(0x100)
+#define EPDC_UPD_STRIDE			(0x110)
 #define EPDC_UPD_CORD			(0x120)
 #define EPDC_UPD_SIZE			(0x140)
 #define EPDC_UPD_CTRL			(0x160)
 #define EPDC_UPD_FIXED			(0x180)
 #define EPDC_TEMP			(0x1a0)
+#define EPDC_AUTOWV_LUT			(0x1C0)
 #define EPDC_TCE_CTRL			(0x200)
 #define EPDC_TCE_SDCFG			(0x220)
 #define EPDC_TCE_GDCFG			(0x240)
@@ -59,6 +61,24 @@
 #define EPDC_TCE_TIMING1		(0x300)
 #define EPDC_TCE_TIMING2		(0x310)
 #define EPDC_TCE_TIMING3		(0x320)
+#define EPDC_PIGEON_CTRL0		(0x380)
+#define EPDC_PIGEON_CTRL1		(0x390)
+#define EPDC_IRQ_MASK1			(0x3C0)
+#define EPDC_IRQ_MASK1_SET		(0x3C4)
+#define EPDC_IRQ_MASK1_CLR		(0x3C8)
+#define EPDC_IRQ_MASK1_TOG		(0x3CC)
+#define EPDC_IRQ_MASK2			(0x3D0)
+#define EPDC_IRQ_MASK2_SET		(0x3D4)
+#define EPDC_IRQ_MASK2_CLR		(0x3D8)
+#define EPDC_IRQ_MASK2_TOG		(0x3DC)
+#define EPDC_IRQ1			(0x3E0)
+#define EPDC_IRQ1_SET			(0x3E4)
+#define EPDC_IRQ1_CLR			(0x3E8)
+#define EPDC_IRQ1_TOG			(0x3EC)
+#define EPDC_IRQ2			(0x3F0)
+#define EPDC_IRQ2_SET			(0x3F4)
+#define EPDC_IRQ2_CLR			(0x3F8)
+#define EPDC_IRQ2_TOG			(0x3FC)
 #define EPDC_IRQ_MASK			(0x400)
 #define EPDC_IRQ_MASK_SET		(0x404)
 #define EPDC_IRQ_MASK_CLR		(0x408)
@@ -71,31 +91,85 @@
 #define EPDC_STATUS_LUTS_SET		(0x444)
 #define EPDC_STATUS_LUTS_CLR		(0x448)
 #define EPDC_STATUS_LUTS_TOG		(0x44c)
+#define EPDC_STATUS_LUTS2		(0x450)
+#define EPDC_STATUS_LUTS2_SET		(0x454)
+#define EPDC_STATUS_LUTS2_CLR		(0x458)
+#define EPDC_STATUS_LUTS2_TOG		(0x45C)
 #define EPDC_STATUS_NEXTLUT		(0x460)
 #define EPDC_STATUS_COL			(0x480)
+#define EPDC_STATUS_COL2		(0x490)
 #define EPDC_STATUS			(0x4a0)
 #define EPDC_STATUS_SET			(0x4a4)
 #define EPDC_STATUS_CLR			(0x4a8)
 #define EPDC_STATUS_TOG			(0x4ac)
+#define EPDC_UPD_COL_CORD		(0x4C0)
+#define EPDC_UPD_COL_SIZE		(0x4E0)
 #define EPDC_DEBUG			(0x500)
-#define EPDC_DEBUG_LUT0			(0x540)
-#define EPDC_DEBUG_LUT1			(0x550)
-#define EPDC_DEBUG_LUT2			(0x560)
-#define EPDC_DEBUG_LUT3			(0x570)
-#define EPDC_DEBUG_LUT4			(0x580)
-#define EPDC_DEBUG_LUT5			(0x590)
-#define EPDC_DEBUG_LUT6			(0x5a0)
-#define EPDC_DEBUG_LUT7			(0x5b0)
-#define EPDC_DEBUG_LUT8			(0x5c0)
-#define EPDC_DEBUG_LUT9			(0x5d0)
-#define EPDC_DEBUG_LUT10		(0x5e0)
-#define EPDC_DEBUG_LUT11		(0x5f0)
-#define EPDC_DEBUG_LUT12		(0x600)
-#define EPDC_DEBUG_LUT13		(0x610)
-#define EPDC_DEBUG_LUT14		(0x620)
-#define EPDC_DEBUG_LUT15		(0x630)
+#define EPDC_DEBUG_LUT			(0x530)
+#define EPDC_HIST1_PARAM		(0x600)
+#define EPDC_HIST2_PARAM		(0x610)
+#define EPDC_HIST4_PARAM		(0x620)
+#define EPDC_HIST8_PARAM0		(0x630)
+#define EPDC_HIST8_PARAM1		(0x640)
+#define EPDC_HIST16_PARAM0		(0x650)
+#define EPDC_HIST16_PARAM1		(0x660)
+#define EPDC_HIST16_PARAM2		(0x670)
+#define EPDC_HIST16_PARAM3		(0x680)
 #define EPDC_GPIO			(0x700)
 #define EPDC_VERSION			(0x7f0)
+#define EPDC_PIGEON_0_0			(0x800)
+#define EPDC_PIGEON_0_1			(0x810)
+#define EPDC_PIGEON_0_2			(0x820)
+#define EPDC_PIGEON_1_0			(0x840)
+#define EPDC_PIGEON_1_1			(0x850)
+#define EPDC_PIGEON_1_2			(0x860)
+#define EPDC_PIGEON_2_0			(0x880)
+#define EPDC_PIGEON_2_1			(0x890)
+#define EPDC_PIGEON_2_2			(0x8A0)
+#define EPDC_PIGEON_3_0			(0x8C0)
+#define EPDC_PIGEON_3_1			(0x8D0)
+#define EPDC_PIGEON_3_2			(0x8E0)
+#define EPDC_PIGEON_4_0			(0x900)
+#define EPDC_PIGEON_4_1			(0x910)
+#define EPDC_PIGEON_4_2			(0x920)
+#define EPDC_PIGEON_5_0			(0x940)
+#define EPDC_PIGEON_5_1			(0x950)
+#define EPDC_PIGEON_5_2			(0x960)
+#define EPDC_PIGEON_6_0			(0x980)
+#define EPDC_PIGEON_6_1			(0x990)
+#define EPDC_PIGEON_6_2			(0x9A0)
+#define EPDC_PIGEON_7_0			(0x9C0)
+#define EPDC_PIGEON_7_1			(0x9D0)
+#define EPDC_PIGEON_7_2			(0x9E0)
+#define EPDC_PIGEON_8_0			(0xA00)
+#define EPDC_PIGEON_8_1			(0xA10)
+#define EPDC_PIGEON_8_2			(0xA20)
+#define EPDC_PIGEON_9_0			(0xA40)
+#define EPDC_PIGEON_9_1			(0xA50)
+#define EPDC_PIGEON_9_2			(0xA60)
+#define EPDC_PIGEON_10_0		(0xA80)
+#define EPDC_PIGEON_10_1		(0xA90)
+#define EPDC_PIGEON_10_2		(0xAA0)
+#define EPDC_PIGEON_11_0		(0xAC0)
+#define EPDC_PIGEON_11_1		(0xAD0)
+#define EPDC_PIGEON_11_2		(0xAE0)
+#define EPDC_PIGEON_12_0		(0xB00)
+#define EPDC_PIGEON_12_1		(0xB10)
+#define EPDC_PIGEON_12_2		(0xB20)
+#define EPDC_PIGEON_13_0		(0xB40)
+#define EPDC_PIGEON_13_1		(0xB50)
+#define EPDC_PIGEON_13_2		(0xB60)
+#define EPDC_PIGEON_14_0		(0xB80)
+#define EPDC_PIGEON_14_1		(0xB90)
+#define EPDC_PIGEON_14_2		(0xBA0)
+#define EPDC_PIGEON_15_0		(0xBC0)
+#define EPDC_PIGEON_15_1		(0xBD0)
+#define EPDC_PIGEON_15_2		(0xBE0)
+#define EPDC_WB_ADDR_TCE		(0xC10)
+
+/*
+ * Register field definitions
+ */
 
 enum {
 	/* EPDC_CTRL field values */
@@ -161,6 +235,9 @@ enum {
 	EPDC_UPD_CTRL_LUT_SEL_OFFSET = 16,
 	EPDC_UPD_CTRL_WAVEFORM_MODE_MASK = 0xff00,
 	EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET = 8,
+	EPDC_UPD_CTRL_AUTOWV_PAUSE = 0x8,
+	EPDC_UPD_CTRL_AUTOWV = 0x4,
+	EPDC_UPD_CTRL_DRY_RUN = 0x2,
 	EPDC_UPD_CTRL_UPDATE_MODE_FULL = 0x1,
 
 	/* EPDC_UPD_FIXED field values */
@@ -171,6 +248,12 @@ enum {
 	EPDC_UPD_FIXED_FIXCP_MASK = 0xff,
 	EPDC_UPD_FIXED_FIXCP_OFFSET = 0,
 
+	/* EPDC_AUTOWV_LUT field values */
+	EPDC_AUTOWV_LUT_DATA_MASK = 0xFF0000,
+	EPDC_AUTOWV_LUT_DATA_OFFSET = 16,
+	EPDC_AUTOWV_LUT_ADDR_MASK = 0xFF,
+	EPDC_AUTOWV_LUT_ADDR_OFFSET = 0,
+
 	/* EPDC_TCE_CTRL field values */
 	EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK = 0x1ff0000,
 	EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET = 16,
@@ -273,27 +356,88 @@ enum {
 	EPDC_IRQ_FRAME_END_IRQ = 0x80000,
 	EPDC_IRQ_BUS_ERROR_IRQ = 0x100000,
 	EPDC_IRQ_TCE_IDLE_IRQ = 0x200000,
+	EPDC_IRQ_UPD_DONE_IRQ = 0x400000,
+	EPDC_IRQ_PWR_IRQ = 0x800000,
 
 	/* EPDC_STATUS_NEXTLUT field values */
 	EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID = 0x100,
-	EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK = 0xf,
+	EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK = 0x3F,
 	EPDC_STATUS_NEXTLUT_NEXT_LUT_OFFSET = 0,
 
 	/* EPDC_STATUS field values */
+	EPDC_STATUS_HISTOGRAM_CP_MASK = 0x1F0000,
+	EPDC_STATUS_HISTOGRAM_CP_OFFSET = 16,
+	EPDC_STATUS_HISTOGRAM_NP_MASK = 0x1F00,
+	EPDC_STATUS_HISTOGRAM_NP_OFFSET = 8,
+	EPDC_STATUS_UPD_VOID = 0x8,
 	EPDC_STATUS_LUTS_UNDERRUN = 0x4,
 	EPDC_STATUS_LUTS_BUSY = 0x2,
 	EPDC_STATUS_WB_BUSY = 0x1,
 
+	/* EPDC_UPD_COL_CORD field values */
+	EPDC_UPD_COL_CORD_YCORD_MASK = 0x1FFF0000,
+	EPDC_UPD_COL_CORD_YCORD_OFFSET = 16,
+	EPDC_UPD_COL_CORD_XCORD_MASK = 0x1FFF,
+	EPDC_UPD_COL_CORD_XCORD_OFFSET = 0,
+
+	/* EPDC_UPD_COL_SIZE field values */
+	EPDC_UPD_COL_SIZE_HEIGHT_MASK = 0x1FFF0000,
+	EPDC_UPD_COL_SIZE_HEIGHT_OFFSET = 16,
+	EPDC_UPD_COL_SIZE_WIDTH_MASK = 0x1FFF,
+	EPDC_UPD_COL_SIZE_WIDTH_OFFSET = 0,
+
 	/* EPDC_DEBUG field values */
 	EPDC_DEBUG_UNDERRUN_RECOVER = 0x2,
 	EPDC_DEBUG_COLLISION_OFF = 0x1,
 
+/* EPDC_HISTx_PARAM field values */
+	EPDC_HIST_PARAM_VALUE0_MASK = 0x1F,
+	EPDC_HIST_PARAM_VALUE0_OFFSET = 0,
+	EPDC_HIST_PARAM_VALUE1_MASK = 0x1F00,
+	EPDC_HIST_PARAM_VALUE1_OFFSET = 8,
+	EPDC_HIST_PARAM_VALUE2_MASK = 0x1F0000,
+	EPDC_HIST_PARAM_VALUE2_OFFSET = 16,
+	EPDC_HIST_PARAM_VALUE3_MASK = 0x1F000000,
+	EPDC_HIST_PARAM_VALUE3_OFFSET = 24,
+	EPDC_HIST_PARAM_VALUE4_MASK = 0x1F,
+	EPDC_HIST_PARAM_VALUE4_OFFSET = 0,
+	EPDC_HIST_PARAM_VALUE5_MASK = 0x1F00,
+	EPDC_HIST_PARAM_VALUE5_OFFSET = 8,
+	EPDC_HIST_PARAM_VALUE6_MASK = 0x1F0000,
+	EPDC_HIST_PARAM_VALUE6_OFFSET = 16,
+	EPDC_HIST_PARAM_VALUE7_MASK = 0x1F000000,
+	EPDC_HIST_PARAM_VALUE7_OFFSET = 24,
+	EPDC_HIST_PARAM_VALUE8_MASK = 0x1F,
+	EPDC_HIST_PARAM_VALUE8_OFFSET = 0,
+	EPDC_HIST_PARAM_VALUE9_MASK = 0x1F00,
+	EPDC_HIST_PARAM_VALUE9_OFFSET = 8,
+	EPDC_HIST_PARAM_VALUE10_MASK = 0x1F0000,
+	EPDC_HIST_PARAM_VALUE10_OFFSET = 16,
+	EPDC_HIST_PARAM_VALUE11_MASK = 0x1F000000,
+	EPDC_HIST_PARAM_VALUE11_OFFSET = 24,
+	EPDC_HIST_PARAM_VALUE12_MASK = 0x1F,
+	EPDC_HIST_PARAM_VALUE12_OFFSET = 0,
+	EPDC_HIST_PARAM_VALUE13_MASK = 0x1F00,
+	EPDC_HIST_PARAM_VALUE13_OFFSET = 8,
+	EPDC_HIST_PARAM_VALUE14_MASK = 0x1F0000,
+	EPDC_HIST_PARAM_VALUE14_OFFSET = 16,
+	EPDC_HIST_PARAM_VALUE15_MASK = 0x1F000000,
+	EPDC_HIST_PARAM_VALUE15_OFFSET = 24,
+
 	/* EPDC_GPIO field values */
 	EPDC_GPIO_PWRCOM = 0x40,
 	EPDC_GPIO_PWRCTRL_MASK = 0x3c,
 	EPDC_GPIO_PWRCTRL_OFFSET = 2,
 	EPDC_GPIO_BDR_MASK = 0x3,
 	EPDC_GPIO_BDR_OFFSET = 0,
+
+	/* EPDC_VERSION field values */
+	EPDC_VERSION_MAJOR_MASK = 0xFF000000,
+	EPDC_VERSION_MAJOR_OFFSET = 24,
+	EPDC_VERSION_MINOR_MASK = 0xFF0000,
+	EPDC_VERSION_MINOR_OFFSET = 16,
+	EPDC_VERSION_STEP_MASK = 0xFFFF,
+	EPDC_VERSION_STEP_OFFSET = 0,
 };
 
 #endif