diff options
author | Liu Ying <Ying.Liu@freescale.com> | 2012-10-06 22:16:04 +0800 |
---|---|---|
committer | Dirk Behme <dirk.behme@gmail.com> | 2012-11-11 11:42:28 +0100 |
commit | 5c1ebe611c4453e085966bb206f53cbea0aad6b8 (patch) | |
tree | f1c2d974378fa48380d78b4aa9a37d0dcfde46b1 /drivers | |
parent | 68d5b543b2875a3a43fe2f9920032a6bd86895cc (diff) |
ipu common: reset ipuv3 correctly
This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
A timeout mechanism is added to stop polling
on the bit status in case the bit could not be
cleared by the hardware automatically within
10 millisecond.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/video/ipu_common.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c index 0f2d113a6f1..ad4af5283a9 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/ipu_common.c @@ -94,6 +94,7 @@ struct ipu_ch_param { temp1; \ }) +#define IPU_SW_RST_TOUT_USEC (10000) void clk_enable(struct clk *clk) { @@ -398,11 +399,20 @@ void ipu_reset(void) { u32 *reg; u32 value; + int timeout = IPU_SW_RST_TOUT_USEC; reg = (u32 *)SRC_BASE_ADDR; value = __raw_readl(reg); value = value | SW_IPU_RST; __raw_writel(value, reg); + + while (__raw_readl(reg) & SW_IPU_RST) { + udelay(1); + if (!(timeout--)) { + printf("ipu software reset timeout\n"); + break; + } + }; } /* |