LogicPD Support for OMAP3/DM3/AM3 boards 2.1 Update

11 files changed, 407 insertions, 13 deletions

diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 9d945a042a9..c585f332a7c 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -25,6 +25,8 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)libdma.o
 
+COBJS-$(CONFIG_OMAP_DMA) += omap3_dma.o
+
 COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
 COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o
 
diff --git a/drivers/dma/omap3_dma.c b/drivers/dma/omap3_dma.c
new file mode 100644
index 00000000000..869e686d997
--- /dev/null
+++ b/drivers/dma/omap3_dma.c
@@ -0,0 +1,242 @@
+/* Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz <at> corscience.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This is a basic implementation of the SDMA/DMA4 controller of OMAP3
+ * Tested on Silicon Revision major:0x4 minor:0x0
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dma.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+static struct dma4 *dma4_cfg = (struct dma4 *)OMAP34XX_DMA4_BASE;
+uint32_t dma_active; /* if a transfer is started the respective
+	bit is set for the logical channel */
+
+/* Initial config of omap dma */
+void omap3_dma_init(void)
+{
+	dma_active = 0;
+	writel(~0, &dma4_cfg->irqenable_l[0]);
+}
+
+/* Check if we have the given channel
+ * PARAMETERS:
+ * chan: Channel number
+ *
+ * RETURN of non-zero means error */
+static inline int check_channel(uint32_t chan)
+{
+	if (chan < CHAN_NR_MIN || chan > CHAN_NR_MAX)
+		return -EINVAL;
+	return 0;
+}
+
+static inline void reset_irq(uint32_t chan)
+{
+	/* reset IRQ reason */
+#if 1
+	writel(CSR_ALL_MASK, &dma4_cfg->chan[chan].csr);
+#else
+	writel(0x1DFE, &dma4_cfg->chan[chan].csr);
+#endif
+	/* reset IRQ */
+	writel((1 << chan), &dma4_cfg->irqstatus_l[0]);
+	dma_active &= ~(1 << chan);
+}
+
+/* Set Source, Destination and Size of DMA transfer for the
+ * specified channel.
+ * PARAMETERS:
+ * chan: channel to use
+ * src: source of the transfer
+ * dst: destination of the transfer
+ * sze: Size of the transfer
+ *
+ * RETURN of non-zero means error */
+int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
+		uint32_t sze)
+{
+	if (check_channel(chan))
+		return -EINVAL;
+	/* CDSA0 */
+	writel((uint32_t)src, &dma4_cfg->chan[chan].cssa);
+	writel((uint32_t)dst, &dma4_cfg->chan[chan].cdsa);
+	writel(sze, &dma4_cfg->chan[chan].cen);
+	return 0;
+}
+
+/* Start the DMA transfer */
+int omap3_dma_start_transfer(uint32_t chan)
+{
+	uint32_t val;
+
+	if (check_channel(chan))
+		return -EINVAL;
+
+	val = readl(&dma4_cfg->chan[chan].ccr);
+	/* Test for channel already in use */
+	if (val & CCR_ENABLE_ENABLE) {
+		printf("%s: ccr %x, returning -EBUSY\n", __FUNCTION__, val);
+		return -EBUSY;
+	}
+
+	writel((val | CCR_ENABLE_ENABLE), &dma4_cfg->chan[chan].ccr);
+	dma_active |= (1 << chan);
+	debug("started transfer...\n");
+	return 0;
+}
+
+void omap3_dma_channel_init(int channel, int next_channel, int csdp_size,
+			int ccr_src_amode, int ccr_dst_amode)
+{
+	struct dma4_chan cfg;
+
+	/* config the channel */
+	omap3_dma_get_conf_chan(channel, &cfg);
+#if 1
+	cfg.csdp = CSDP_SRC_BURST_EN_64BYTES |
+		CSDP_DST_BURST_EN_64BYTES | CSDP_DST_ENDIAN_LOCK_ADAPT |
+		CSDP_DST_ENDIAN_LITTLE | CSDP_SRC_ENDIAN_LOCK_ADAPT |
+		CSDP_SRC_ENDIAN_LITTLE;
+	cfg.cfn = 1;
+	cfg.ccr = CCR_READ_PRIORITY_HIGH;
+	cfg.csdp |= csdp_size;
+	cfg.ccr |= ccr_src_amode;
+	cfg.ccr |= ccr_dst_amode;
+#else
+	cfg.cdsp |= CSDP_DATA_TYPE_32BIT;
+	cfg.csdp = CSDP_DATA_TYPE_32BIT | CSDP_SRC_BURST_EN_64BYTES |
+		CSDP_DST_BURST_EN_64BYTES | CSDP_DST_ENDIAN_LOCK_ADAPT |
+		CSDP_DST_ENDIAN_LITTLE | CSDP_SRC_ENDIAN_LOCK_ADAPT |
+		CSDP_SRC_ENDIAN_LITTLE;
+	cfg.ccr = CCR_READ_PRIORITY_HIGH | CCR_DST_AMODE_POST_INC;
+	if (src_post_incr)
+	{
+		cfg.ccr |= CCR_SRC_AMODE_CONSTANT;
+	}
+	else
+	{
+		cfg.ccr |= CCR_SRC_AMODE_POST_INC;
+	}
+#endif
+	cfg.cicr = CICR_BLOCK_IE | CICR_MISALIGNED_ERR_IE
+		| CICR_SUPERVISOR_ERR_IE | CICR_TRANS_ERR_IE;
+
+	if (next_channel >= 0)
+	{
+		cfg.clnk_ctrl = CLNK_CTRL_ENABLE_LNK | next_channel;
+	}
+	else
+	{
+		cfg.clnk_ctrl = 0;
+	}
+	omap3_dma_set_conf_chan(channel, &cfg);
+}
+
+/* Busy-waiting for a DMA transfer
+ * This has to be called before another transfer is started
+ * PARAMETER
+ * chan: Channel to wait for
+ *
+ * RETURN of non-zero means error*/
+int omap3_dma_wait_for_transfer(uint32_t chan, int chained)
+{
+	uint32_t val;
+
+	if (!chained)
+	{
+		if (!(dma_active & (1 << chan))) {
+			val = readl(&dma4_cfg->irqstatus_l[0]);
+			if (!(val & chan)) {
+				debug("dma: The channel you are trying to wait for "
+					"was never activated - ERROR\n");
+				return -1; /* channel was never active */
+			}
+		}
+	}
+
+	/* all irqs on line 0 */
+	while (!(readl(&dma4_cfg->irqstatus_l[0]) & (1 << chan)))
+		asm("nop");
+
+	val = readl(&dma4_cfg->chan[chan].csr);
+	if ((val & CSR_TRANS_ERR) | (val & CSR_SUPERVISOR_ERR) |
+			(val & CSR_MISALIGNED_ADRS_ERR)) {
+		debug("err code: %X\n", val);
+		debug("dma: transfer error detected\n");
+		reset_irq(chan);
+		return -1;
+	}
+	reset_irq(chan);
+	return 0;
+}
+
+int omap3_dma_transfer(int channel, void *src, void *dst, int size, int flags)
+{
+	int res;
+	res = omap3_dma_conf_transfer(channel, src, dst, (size + 3) / 4);
+	if (res < 0)
+	{
+		printf("omap3_dma_conf_transfer = %d\n", res);
+		return res;
+	}
+	if (flags & FB_DMA_START)
+	{
+		res = omap3_dma_start_transfer(channel);
+		if (res < 0)
+		{
+			printf("omap3_dma_start_transfer = %d\n", res);
+			return res;
+		}
+	}
+	if (flags & FB_DMA_WAIT)
+	{
+		res = omap3_dma_wait_for_transfer(channel, 0);
+	}
+	return res;
+}
+
+/* set channel config to config
+ *
+ * RETURN of non-zero means error */
+int omap3_dma_set_conf_chan(uint32_t chan, struct dma4_chan *config)
+{
+	if (check_channel(chan))
+		return -EINVAL;
+	/* Dinon - Use dma4_chan_padded instead of dma4_chan for
+	 * channel 1 ~ 31 to work */
+	*((struct dma4_chan *)&dma4_cfg->chan[chan]) = *config;
+	return 0;
+}
+
+/* get channel config to config
+ *
+ * RETURN of non-zero means error */
+int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config)
+{
+	if (check_channel(chan))
+		return -EINVAL;
+	/* Dinon - Use dma4_chan_padded instead of dma4_chan for
+	 * channel 1 ~ 31 to work */
+	*config = *((struct dma4_chan *)&dma4_cfg->chan[chan]);
+	return 0;
+}
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index ec02a5d33e8..ca64e37ce68 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -40,6 +40,12 @@ static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;
 static unsigned int bus_initialized[I2C_BUS_MAX];
 static unsigned int current_bus;
 
+int __i2c_mux_bus_pins(int bus)
+{
+	return 0;
+}
+void i2c_mux_bus_pins(int bus) __attribute__ ((weak, alias ("__i2c_mux_bus_pins")));
+
 void i2c_init (int speed, int slaveadd)
 {
 	int psc, fsscll, fssclh;
@@ -143,6 +149,7 @@ void i2c_init (int speed, int slaveadd)
 
 	if (gd->flags & GD_FLG_RELOC)
 		bus_initialized[current_bus] = 1;
+	i2c_mux_bus_pins(current_bus);
 }
 
 static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c
index 83d27918872..3f1252dddba 100644
--- a/drivers/mmc/omap3_mmc.c
+++ b/drivers/mmc/omap3_mmc.c
@@ -30,6 +30,9 @@
 #include <i2c.h>
 #include <twl4030.h>
 #include <asm/io.h>
+#include <asm/arch/dma.h>
+
+#undef CONFIG_OMAP_DMA /* DMA for MMC doesn't work yet */
 
 #include "omap3_mmc.h"
 
@@ -280,11 +283,19 @@ static unsigned char mmc_read_data(unsigned int *output_buf)
 
 			writel(readl(&mmc_base->stat) | BRR_MASK,
 				&mmc_base->stat);
+#ifdef CONFIG_OMAP_DMA
+			/* Invalidate the datacache for the buffer,
+			 * setup the DMA and wait for it to finish */
+			invalidate_dcache_range((unsigned long)output_buf, MMCSD_SECTOR_SIZE);
+
+			omap3_dma_transfer(DMA_CHANNEL_MMC, &mmc_base->data, output_buf, MMCSD_SECTOR_SIZE, FB_DMA_START | FB_DMA_WAIT);
+#else
 			for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) {
 				*output_buf = readl(&mmc_base->data);
 				output_buf++;
 				read_count += 4;
 			}
+#endif
 		}
 
 		if (mmc_stat & BWR_MASK)
@@ -641,6 +652,11 @@ int mmc_legacy_init(int dev)
 	mmc_blk_dev.removable = 0;
 	mmc_blk_dev.block_read = mmc_bread;
 
+#ifdef CONFIG_OMAP_DMA
+	omap3_dma_channel_init(DMA_CHANNEL_MMC, -1, CSDP_DATA_TYPE_32BIT, CCR_SRC_AMODE_CONSTANT, CCR_DST_AMODE_POST_INC);
+#endif
+
 	fat_register_device(&mmc_blk_dev, 1);
+
 	return 0;
 }
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index d987f4c85c8..8a623e84808 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -77,17 +77,22 @@ static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand,
 
 }
 
+unsigned int mtd_nand_size;
+unsigned int nand_size(void)
+{
+	return mtd_nand_size;
+}
+
 void nand_init(void)
 {
 	int i;
-	unsigned int size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
 		nand_init_chip(&nand_info[i], &nand_chip[i], base_address[i]);
-		size += nand_info[i].size / 1024;
+		mtd_nand_size += nand_info[i].size / 1024;
 		if (nand_curr_device == -1)
 			nand_curr_device = i;
 	}
-	printf("%u MiB\n", size / 1024);
+	printf("%u MiB\n", mtd_nand_size / 1024);
 
 #ifdef CONFIG_SYS_NAND_SELECT_DEVICE
 	/*
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index 82e661d39c9..c9f1283fa00 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -510,7 +510,8 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 		return -EINVAL;
 	}
 
-	if (!need_skip && !withoob) {
+	/* Write one page at a time since need to update percentage */
+	if (0 && !need_skip && !withoob) {
 		rval = nand_write (nand, offset, length, buffer);
 		if (rval == 0)
 			return 0;
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index d5ee9bc5836..1a636cad236 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -31,8 +31,49 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/nand_bch.h>
 #include <nand.h>
+#include <asm/arch/dma.h>
+
 
 static uint8_t cs;
+
+#ifdef CONFIG_OMAP_DMA
+void omap_dma_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	int i;
+	struct nand_chip *chip = mtd->priv;
+	u16 *p = (u16 *) buf;
+
+//	printf("%s: len %u\n", __FUNCTION__, len);
+
+
+	/* If request is too small, read it by hand */
+	if (len <= 32) {
+		len >>= 1;
+		for (i = 0; i < len; i+=8) {
+			*p++ = readw(chip->IO_ADDR_R);
+			*p++ = readw(chip->IO_ADDR_R);
+			*p++ = readw(chip->IO_ADDR_R);
+			*p++ = readw(chip->IO_ADDR_R);
+			*p++ = readw(chip->IO_ADDR_R);
+			*p++ = readw(chip->IO_ADDR_R);
+			*p++ = readw(chip->IO_ADDR_R);
+			*p++ = readw(chip->IO_ADDR_R);
+		}
+		for (; i < len; ++i)
+			*p++ = readw(chip->IO_ADDR_R);
+		return;
+	}
+
+	/* Invalidate the datacache for the buffer, program the DMA and wait
+	 * for it to finish */
+	invalidate_dcache_range((unsigned long)p, (unsigned long)(p + len));
+
+
+	/* Transfer the data(and wait to complete) */
+	omap3_dma_transfer(DMA_CHANNEL_NAND, chip->IO_ADDR_R, buf, len, FB_DMA_START | FB_DMA_WAIT);
+}
+#endif
+
 static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
 static struct nand_ecclayout chip_nand_oob = GPMC_NAND_CHIP_ECC_LAYOUT;
 
@@ -282,7 +323,7 @@ int omap_nand_chip_has_ecc(void)
 	if (nand_curr_device < 0 ||
 	    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
 	    !nand_info[nand_curr_device].name) {
-		printf("Error: Can't switch ecc, no devices available\n");
+		/* If no device, no in-chip ECC! */
 		return 0;
 	}
 
@@ -572,10 +613,8 @@ void omap_nand_switch_ecc(enum omap_nand_ecc_mode mode)
 
 	if (nand_curr_device < 0 ||
 	    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
-	    !nand_info[nand_curr_device].name) {
-		printf("Error: Can't switch ecc, no devices available\n");
+	    !nand_info[nand_curr_device].name)
 		return;
-	}
 
 	mtd = &nand_info[nand_curr_device];
 	nand = mtd->priv;
@@ -664,6 +703,13 @@ void omap_nand_switch_ecc(enum omap_nand_ecc_mode mode)
 		nand->ecc.hwctl = omap_enable_chip_hwecc;
 		nand->ecc.correct = omap_correct_chip_hwecc;
 		nand->ecc.read_oob = omap_read_oob_chipecc;
+#ifdef CONFIG_OMAP_DMA
+		omap3_dma_channel_init(DMA_CHANNEL_NAND, -1, CSDP_DATA_TYPE_32BIT, CCR_SRC_AMODE_CONSTANT, CCR_DST_AMODE_POST_INC);
+		if (nand->options & NAND_BUSWIDTH_16)
+			nand->read_buf = omap_dma_read_buf16;
+		else
+			printf("%s: Huh? not 16-bit for DMA\n", __FUNCTION__);
+#endif
 		nand->ecc.mode = NAND_ECC_CHIP; /* internal to chip */
 		nand->ecc.layout = &chip_nand_oob;
 		if (nand->options & NAND_BUSWIDTH_16)
diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c
index cf79161aaf3..b62ed176d25 100644
--- a/drivers/power/twl4030.c
+++ b/drivers/power/twl4030.c
@@ -86,7 +86,7 @@ void twl4030_power_init(void)
 	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VPLL2_DEDICATED,
 				TWL4030_PM_RECEIVER_VPLL2_VSEL_18,
 				TWL4030_PM_RECEIVER_VPLL2_DEV_GRP,
-				TWL4030_PM_RECEIVER_DEV_GRP_ALL);
+				TWL4030_PM_RECEIVER_DEV_GRP_P1);
 
 	/* set VDAC to 1.8V */
 	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDAC_DEDICATED,
@@ -133,6 +133,46 @@ U_BOOT_CMD(poweroff, 1, 1, do_poweroff,
 );
 
 #ifdef CONFIG_TWL4030_CHARGING
+/* Enable the battery backup charger */
+int twl4030_enable_bb_charging(unsigned int millivolts, unsigned int microamps)
+{
+	u8 val;
+
+	if (millivolts >= 3200)
+		val = 0x0c;
+	else if (millivolts >= 3100)
+		val = 0x08;
+	else if (millivolts >= 3000)
+		val = 0x04;
+	else if (millivolts < 2500) {
+		val = 0;
+		goto write_it;
+	}
+	if (microamps >= 1000)
+		val |= 0x03;
+	else if (microamps >= 500)
+		val |= 0x02;
+	else if (microamps >= 150)
+		val |= 0x01;
+	else if (microamps < 25) {
+		val = 0;
+		goto write_it;
+	}
+
+	val |= 0x10; 	/* set BBCHEN */
+
+	printf("Enable battery backup charger (BB_CFG = 0x%02x)\n", val);
+write_it:
+	if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, val,
+					TWL4030_PM_RECEIVER_BB_CFG)) {
+		printf("Error:TWL4030: failed to write BB_CFG\n");
+		return 1;
+	}
+	return 0;
+}
+
+
+/* Enable AC charging */
 int twl4030_enable_charging(void)
 {
 	u8 val = 0;
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 8eeb48fb2a9..a44bd97ecb1 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -53,9 +53,22 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
 #endif /* CONFIG_OMAP */
 }
 
+#ifdef CONFIG_SERIAL_OUTPUT_FIFO
+/* Flush transmit fifo and holding register */
+void NS16550_flush_tx_fifo(NS16550_t com_port)
+{
+	while ((serial_in(&com_port->lsr) & UART_LSR_TEMT) == 0)
+		;
+}
+#endif
+
 #ifndef CONFIG_NS16550_MIN_FUNCTIONS
 void NS16550_reinit (NS16550_t com_port, int baud_divisor)
 {
+#ifdef CONFIG_SERIAL_OUTPUT_FIFO
+	/* flush output fifo before changing baudrate */
+	NS16550_flush_tx_fifo(com_port);
+#endif
 	serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
 	serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
 	serial_out(0, &com_port->dll);
@@ -72,7 +85,13 @@ void NS16550_reinit (NS16550_t com_port, int baud_divisor)
 
 void NS16550_putc (NS16550_t com_port, char c)
 {
+#ifdef CONFIG_SERIAL_OUTPUT_FIFO
+	/* Wait for some room in the fifo */
+	while ((serial_in(&com_port->ssr) & UART_SSR_TX_FIFO_FULL));
+#else
+	/* Wait for Xmit holding register to be empty */
 	while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0);
+#endif
 	serial_out(c, &com_port->thr);
 
 	/*
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 4032dfde748..913432c27e3 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -215,6 +215,18 @@ _serial_puts (const char *s,const int port)
 	}
 }
 
+#ifdef CONFIG_SERIAL_OUTPUT_FIFO
+void
+_serial_flush_output(const int port)
+{
+	NS16550_flush_tx_fifo(PORT);
+}
+#else
+void
+_serial_flush_output(void)
+{
+}
+#endif
 
 int
 _serial_getc(const int port)
diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c
index 6b33250d3a5..8d629d3a040 100644
--- a/drivers/video/omap3_dss.c
+++ b/drivers/video/omap3_dss.c
@@ -30,6 +30,7 @@
 #include <asm/arch/dss.h>
 #include <asm/arch/sys_proto.h>
 
+#undef DEBUG
 #ifdef DEBUG
 #define DSS_DBG_CLK(fmt, ...) printf(fmt, ##__VA_ARGS__)
 #else
@@ -217,11 +218,12 @@ void dispc_find_clk_divs(int is_tft, unsigned long req_pck, unsigned long fck,
 	}
 
 found:
+
 	cinfo->lck_div = best_ld;
 	cinfo->pck_div = best_pd;
 	cinfo->lck = fck / cinfo->lck_div;
 	cinfo->pck = cinfo->lck / cinfo->pck_div;
-	DSS_DBG_CLK("%s: %d best_ld %u best_pd %u pck %lu\n", __FUNCTION__, __LINE__, best_ld, best_pd, cinfo->pck);
+	DSS_DBG_CLK("%s:%d fck %lu best_ld %u best_pd %u pck %lu\n", __FUNCTION__, __LINE__, fck, best_ld, best_pd, cinfo->pck);
 }
 
 int omap3_dss_calc_divisor(int is_tft, unsigned int req_pck,
@@ -269,9 +271,11 @@ int omap3_dss_calc_divisor(int is_tft, unsigned int req_pck,
 
 		dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 
-		DSS_DBG_CLK("%s:%d cur.pck %u < best_pck %u?\n", __FUNCTION__, __LINE__,
-			abs(cur_dispc.pck - req_pck),
-			abs(best_dispc.pck - req_pck));
+		DSS_DBG_CLK("%s:%d cur.pck(%d-%d) %u < best_pck(%d-%d) %u?\n", __FUNCTION__, __LINE__,
+				cur_dispc.pck, req_pck,
+				abs(cur_dispc.pck - req_pck),
+				best_dispc.pck, req_pck,
+				abs(best_dispc.pck - req_pck));
 
 		if (abs(cur_dispc.pck - req_pck) <
 			abs(best_dispc.pck - req_pck)) {