Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

* 'master' of git://git.denx.de/u-boot-mpc85xx:
  mpc85xx: support for Freescale COM Express P2020
  arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warning
  mpc85xx: support board-specific reset function
  powerpc/85xx: verify the localbus device tree address before booting the OS
  mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification
  powerpc/p3060qds: Add board related support for P3060QDS platform
  powerpc/85xx: clean up and document the QE/FMAN microcode macros
  powerpc/85xx: always implement the work-around for Erratum SATA_A001
  powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h
  powerpc/85xx: Add workaround for erratum A-003474
  powerpc/85xx: fixup flexcan device tree clock-frequency
  powerpc/85xx: Add workaround for erratum CPU-A003999

4 files changed, 19 insertions, 39 deletions

diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c
index 6b3517369d..3026adec0d 100644
--- a/drivers/block/fsl_sata.c
+++ b/drivers/block/fsl_sata.c
@@ -197,27 +197,6 @@ int init_sata(int dev)
 	/* Wait the controller offline */
 	ata_wait_register(&reg->hstatus, HSTATUS_ONOFF, 0, 1000);
 
-#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
-	/*
-	 * For P1022/1013 Rev1.0 silicon, after power on SATA host
-	 * controller is configured in legacy mode instead of the
-	 * expected enterprise mode. software needs to clear bit[28]
-	 * of HControl register to change to enterprise mode from
-	 * legacy mode.
-	 */
-	{
-		u32 svr = get_svr();
-		if (IS_SVR_REV(svr, 1, 0) &&
-		    ((SVR_SOC_VER(svr) == SVR_P1022) ||
-		     (SVR_SOC_VER(svr) == SVR_P1022_E) ||
-		     (SVR_SOC_VER(svr) == SVR_P1013) ||
-		     (SVR_SOC_VER(svr) == SVR_P1013_E))) {
-			out_le32(&reg->hstatus, 0x20000000);
-			out_le32(&reg->hcontrol, 0x00000100);
-		}
-	}
-#endif
-
 	/* Set the command header base address to CHBA register to tell DMA */
 	out_le32(&reg->chba, (u32)cmd_hdr & ~0x3);
 
diff --git a/drivers/block/fsl_sata.h b/drivers/block/fsl_sata.h
index 576efaf6f5..cecff68da3 100644
--- a/drivers/block/fsl_sata.h
+++ b/drivers/block/fsl_sata.h
@@ -103,6 +103,7 @@ typedef struct fsl_sata_reg {
 */
 #define HCONTROL_ONOFF			0x80000000 /* Online or offline request */
 #define HCONTROL_FORCE_OFFLINE		0x40000000 /* Force offline request */
+#define HCONTROL_ENTERPRISE_EN		0x10000000 /* Enterprise mode enabled */
 #define HCONTROL_HDR_SNOOP		0x00000400 /* Command header snoop */
 #define HCONTROL_PMP_ATTACHED		0x00000200 /* Port multiplier attached */
 
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 846c37249b..0b8c33fb7a 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -25,11 +25,11 @@
 #include "fm.h"
 #include "../../qe/qe.h"		/* For struct qe_firmware */
 
-#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #include <nand.h>
 #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
 #include <spi_flash.h>
-#elif defined(CONFIG_SYS_QE_FW_IN_MMC)
+#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
 #include <mmc.h>
 #endif
 
@@ -363,21 +363,21 @@ int fm_init_common(int index, struct ccsr_fman *reg)
 {
 	int rc;
 	char env_addr[32];
-#if defined(CONFIG_SYS_FMAN_FW_ADDR)
-	void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
-#elif defined(CONFIG_SYS_QE_FW_IN_NAND)
-	size_t fw_length = CONFIG_SYS_FMAN_FW_LENGTH;
-	void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH);
+#if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
+	void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR;
+#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
+	size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
+	void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
 
-	rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
+	rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_ADDR,
 		       &fw_length, (u_char *)addr);
 	if (rc == -EUCLEAN) {
 		printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
-			CONFIG_SYS_QE_FW_IN_NAND, rc);
+			CONFIG_SYS_QE_FMAN_FW_ADDR, rc);
 	}
 #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
 	struct spi_flash *ucode_flash;
-	void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH);
+	void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
 	int ret = 0;
 
 	ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
@@ -385,17 +385,17 @@ int fm_init_common(int index, struct ccsr_fman *reg)
 	if (!ucode_flash)
 		printf("SF: probe for ucode failed\n");
 	else {
-		ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FW_IN_SPIFLASH,
-				CONFIG_SYS_FMAN_FW_LENGTH, addr);
+		ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FMAN_FW_ADDR,
+				CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
 		if (ret)
 			printf("SF: read for ucode failed\n");
 		spi_flash_free(ucode_flash);
 	}
-#elif defined(CONFIG_SYS_QE_FW_IN_MMC)
+#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
 	int dev = CONFIG_SYS_MMC_ENV_DEV;
-	void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH);
-	u32 cnt = CONFIG_SYS_FMAN_FW_LENGTH / 512;
-	u32 blk = CONFIG_SYS_QE_FW_IN_MMC / 512;
+	void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+	u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+	u32 blk = CONFIG_SYS_QE_FMAN_FW_ADDR / 512;
 	struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
 
 	if (!mmc)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index c4ec2f4af8..9f711519ed 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -170,11 +170,11 @@ void qe_init(uint qe_base)
 	/* Init the QE IMMR base */
 	qe_immr = (qe_map_t *)qe_base;
 
-#ifdef CONFIG_SYS_QE_FW_ADDR
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NOR
 	/*
 	 * Upload microcode to IRAM for those SOCs which do not have ROM in QE.
 	 */
-	qe_upload_firmware((const struct qe_firmware *) CONFIG_SYS_QE_FW_ADDR);
+	qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR);
 
 	/* enable the microcode in IRAM */
 	out_be32(&qe_immr->iram.iready,QE_IRAM_READY);