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authorYusuke Goda <goda.yusuke@renesas.com>2008-03-05 14:23:26 +0900
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2008-03-28 14:16:12 +0900
commitb55523efff2ae11f0b9ae3cc405893c32eb78156 (patch)
tree5cfe0df041357f05f50f6d327c38656ca79ee9b1 /drivers
parentc2042f5952a686c414031309b8f244513bf578f0 (diff)
sh: Add support SH7780
SH7780 is CPU of Renesas Technology. This CPU has - CPU clock 400MHz - PCI support - DDR-SDRAM controller - etc ... Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/serial/serial_sh.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 70fd23ff0a..ecb97bfcf9 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -46,26 +46,28 @@
#define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
#endif
-#if defined(CONFIG_SH4A)
+#if defined(CONFIG_CPU_SH7780) || \
+ defined(CONFIG_CPU_SH7785)
#define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
#define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
#define SCLSR (vu_short *)(SCIF_BASE + 0x28)
#define SCRER (vu_short *)(SCIF_BASE + 0x2C)
#define LSR_ORER 1
-#elif defined (CONFIG_SH4)
+#elif defined(CONFIG_CPU_SH7750) || \
+ defined(CONFIG_CPU_SH7722)
#define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
#define SCLSR (vu_short *)(SCIF_BASE + 0x24)
#define LSR_ORER 1
-#elif defined (CONFIG_SH3)
-#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
+#elif defined(CONFIG_CPU_SH7720)
#define SCLSR (vu_short *)(SCIF_BASE + 0x24)
#define LSR_ORER 0x0200
-#else
+#elif defined(CONFIG_CPU_SH7710)
+ defined(CONFIG_CPU_SH7712)
#define SCLSR SCFSR /* SCSSR */
#define LSR_ORER 1
#endif
-#endif
+/* SCBRR register value setting */
#if defined(CONFIG_CPU_SH7720)
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
#else /* Generic SuperH */