Merge branch 'master' of git://git.denx.de/u-boot-mips

14 files changed, 487 insertions, 99 deletions

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 8f3b96a9736..c05ce2a9efa 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -20,6 +20,14 @@ config SPL_CLK
 	  setting up clocks within SPL, and allows the same drivers to be
 	  used as U-Boot proper.
 
+config CLK_BOSTON
+	def_bool y if TARGET_BOSTON
+	depends on CLK
+	select REGMAP
+	select SYSCON
+	help
+	  Enable this to support the clocks
+
 source "drivers/clk/tegra/Kconfig"
 source "drivers/clk/uniphier/Kconfig"
 source "drivers/clk/exynos/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 778d7486f06..40a5e8cae86 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -15,3 +15,4 @@ obj-y += tegra/
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
 obj-$(CONFIG_CLK_EXYNOS) += exynos/
 obj-$(CONFIG_CLK_AT91) += at91/
+obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
diff --git a/drivers/clk/clk_boston.c b/drivers/clk/clk_boston.c
new file mode 100644
index 00000000000..78f1b759d83
--- /dev/null
+++ b/drivers/clk/clk_boston.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dt-bindings/clock/boston-clock.h>
+#include <regmap.h>
+#include <syscon.h>
+
+struct clk_boston {
+	struct regmap *regmap;
+};
+
+#define BOSTON_PLAT_MMCMDIV		0x30
+# define BOSTON_PLAT_MMCMDIV_CLK0DIV	(0xff << 0)
+# define BOSTON_PLAT_MMCMDIV_INPUT	(0xff << 8)
+# define BOSTON_PLAT_MMCMDIV_MUL	(0xff << 16)
+# define BOSTON_PLAT_MMCMDIV_CLK1DIV	(0xff << 24)
+
+static uint32_t ext_field(uint32_t val, uint32_t mask)
+{
+	return (val & mask) >> (ffs(mask) - 1);
+}
+
+static ulong clk_boston_get_rate(struct clk *clk)
+{
+	struct clk_boston *state = dev_get_platdata(clk->dev);
+	uint32_t in_rate, mul, div;
+	uint mmcmdiv;
+	int err;
+
+	err = regmap_read(state->regmap, BOSTON_PLAT_MMCMDIV, &mmcmdiv);
+	if (err)
+		return 0;
+
+	in_rate = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_INPUT);
+	mul = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_MUL);
+
+	switch (clk->id) {
+	case BOSTON_CLK_SYS:
+		div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK0DIV);
+		break;
+	case BOSTON_CLK_CPU:
+		div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK1DIV);
+		break;
+	default:
+		return 0;
+	}
+
+	return (in_rate * mul * 1000000) / div;
+}
+
+const struct clk_ops clk_boston_ops = {
+	.get_rate = clk_boston_get_rate,
+};
+
+static int clk_boston_ofdata_to_platdata(struct udevice *dev)
+{
+	struct clk_boston *state = dev_get_platdata(dev);
+	struct udevice *syscon;
+	int err;
+
+	err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+					   "regmap", &syscon);
+	if (err) {
+		error("unable to find syscon device\n");
+		return err;
+	}
+
+	state->regmap = syscon_get_regmap(syscon);
+	if (!state->regmap) {
+		error("unable to find regmap\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id clk_boston_match[] = {
+	{
+		.compatible = "img,boston-clock",
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(clk_boston) = {
+	.name = "boston_clock",
+	.id = UCLASS_CLK,
+	.of_match = clk_boston_match,
+	.ofdata_to_platdata = clk_boston_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct clk_boston),
+	.ops = &clk_boston_ops,
+};
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index 6a634e69518..23b6ba78d3b 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -101,36 +101,24 @@ int device_bind_driver_to_node(struct udevice *parent, const char *drv_name,
 
 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 /**
- * driver_check_compatible() - Check if a driver is compatible with this node
+ * driver_check_compatible() - Check if a driver matches a compatible string
  *
- * @param blob:		Device tree pointer
- * @param offset:	Offset of node in device tree
  * @param of_match:	List of compatible strings to match
  * @param of_idp:	Returns the match that was found
- * @return 0 if there is a match, -ENOENT if no match, -ENODEV if the node
- * does not have a compatible string, other error <0 if there is a device
- * tree error
+ * @param compat:	The compatible string to search for
+ * @return 0 if there is a match, -ENOENT if no match
  */
-static int driver_check_compatible(const void *blob, int offset,
-				   const struct udevice_id *of_match,
-				   const struct udevice_id **of_idp)
+static int driver_check_compatible(const struct udevice_id *of_match,
+				   const struct udevice_id **of_idp,
+				   const char *compat)
 {
-	int ret;
-
-	*of_idp = NULL;
 	if (!of_match)
 		return -ENOENT;
 
 	while (of_match->compatible) {
-		ret = fdt_node_check_compatible(blob, offset,
-						of_match->compatible);
-		if (!ret) {
+		if (!strcmp(of_match->compatible, compat)) {
 			*of_idp = of_match;
 			return 0;
-		} else if (ret == -FDT_ERR_NOTFOUND) {
-			return -ENODEV;
-		} else if (ret < 0) {
-			return -EINVAL;
 		}
 		of_match++;
 	}
@@ -147,28 +135,46 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset,
 	struct driver *entry;
 	struct udevice *dev;
 	bool found = false;
-	const char *name;
+	const char *name, *compat_list, *compat;
+	int compat_length, i;
 	int result = 0;
 	int ret = 0;
 
-	dm_dbg("bind node %s\n", fdt_get_name(blob, offset, NULL));
+	name = fdt_get_name(blob, offset, NULL);
+	dm_dbg("bind node %s\n", name);
 	if (devp)
 		*devp = NULL;
-	for (entry = driver; entry != driver + n_ents; entry++) {
-		ret = driver_check_compatible(blob, offset, entry->of_match,
-					      &id);
-		name = fdt_get_name(blob, offset, NULL);
-		if (ret == -ENOENT) {
-			continue;
-		} else if (ret == -ENODEV) {
+
+	compat_list = fdt_getprop(blob, offset, "compatible", &compat_length);
+	if (!compat_list) {
+		if (compat_length == -FDT_ERR_NOTFOUND) {
 			dm_dbg("Device '%s' has no compatible string\n", name);
-			break;
-		} else if (ret) {
-			dm_warn("Device tree error at offset %d\n", offset);
-			result = ret;
-			break;
+			return 0;
 		}
 
+		dm_warn("Device tree error at offset %d\n", offset);
+		return compat_length;
+	}
+
+	/*
+	 * Walk through the compatible string list, attempting to match each
+	 * compatible string in order such that we match in order of priority
+	 * from the first string to the last.
+	 */
+	for (i = 0; i < compat_length; i += strlen(compat) + 1) {
+		compat = compat_list + i;
+		dm_dbg("   - attempt to match compatible string '%s'\n",
+		       compat);
+
+		for (entry = driver; entry != driver + n_ents; entry++) {
+			ret = driver_check_compatible(entry->of_match, &id,
+						      compat);
+			if (!ret)
+				break;
+		}
+		if (entry == driver + n_ents)
+			continue;
+
 		dm_dbg("   - found match at '%s'\n", entry->name);
 		ret = device_bind_with_driver_data(parent, entry, name,
 						   id->data, offset, &dev);
@@ -188,10 +194,8 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset,
 		break;
 	}
 
-	if (!found && !result && ret != -ENODEV) {
-		dm_dbg("No match for node '%s'\n",
-		       fdt_get_name(blob, offset, NULL));
-	}
+	if (!found && !result && ret != -ENODEV)
+		dm_dbg("No match for node '%s'\n", name);
 
 	return result;
 }
diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index 0299ff08793..c68bcba54f1 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -13,6 +13,8 @@
 #include <mapmem.h>
 #include <regmap.h>
 
+#include <asm/io.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct regmap *regmap_alloc_count(int count)
@@ -117,3 +119,21 @@ int regmap_uninit(struct regmap *map)
 
 	return 0;
 }
+
+int regmap_read(struct regmap *map, uint offset, uint *valp)
+{
+	uint32_t *ptr = map_physmem(map->base + offset, 4, MAP_NOCACHE);
+
+	*valp = le32_to_cpu(readl(ptr));
+
+	return 0;
+}
+
+int regmap_write(struct regmap *map, uint offset, uint val)
+{
+	uint32_t *ptr = map_physmem(map->base + offset, 4, MAP_NOCACHE);
+
+	writel(cpu_to_le32(val), ptr);
+
+	return 0;
+}
diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index 01bd9683a7a..2148469abc1 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -95,3 +95,14 @@ UCLASS_DRIVER(syscon) = {
 	.per_device_auto_alloc_size = sizeof(struct syscon_uc_info),
 	.pre_probe = syscon_pre_probe,
 };
+
+static const struct udevice_id generic_syscon_ids[] = {
+	{ .compatible = "syscon" },
+	{ }
+};
+
+U_BOOT_DRIVER(generic_syscon) = {
+	.name	= "syscon",
+	.id	= UCLASS_SYSCON,
+	.of_match = generic_syscon_ids,
+};
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index be3ed73e522..302c005aa13 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -175,7 +175,7 @@ config XILINX_AXIEMAC
 	  This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.
 
 config XILINX_EMACLITE
-	depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
+	depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || MIPS)
 	select PHYLIB
 	select MII
 	bool "Xilinx Ethernetlite"
diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c
index 137818b3907..d40fff0e488 100644
--- a/drivers/net/pch_gbe.c
+++ b/drivers/net/pch_gbe.c
@@ -118,14 +118,14 @@ static void pch_gbe_rx_descs_init(struct udevice *dev)
 	memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM);
 	for (i = 0; i < PCH_GBE_DESC_NUM; i++)
 		rx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev,
-			(u32)(priv->rx_buff[i]));
+			(ulong)(priv->rx_buff[i]));
 
-	writel(dm_pci_phys_to_mem(priv->dev, (u32)rx_desc),
+	writel(dm_pci_phys_to_mem(priv->dev, (ulong)rx_desc),
 	       &mac_regs->rx_dsc_base);
 	writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1),
 	       &mac_regs->rx_dsc_size);
 
-	writel(dm_pci_phys_to_mem(priv->dev, (u32)(rx_desc + 1)),
+	writel(dm_pci_phys_to_mem(priv->dev, (ulong)(rx_desc + 1)),
 	       &mac_regs->rx_dsc_sw_p);
 }
 
@@ -137,11 +137,11 @@ static void pch_gbe_tx_descs_init(struct udevice *dev)
 
 	memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
 
-	writel(dm_pci_phys_to_mem(priv->dev, (u32)tx_desc),
+	writel(dm_pci_phys_to_mem(priv->dev, (ulong)tx_desc),
 	       &mac_regs->tx_dsc_base);
 	writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1),
 	       &mac_regs->tx_dsc_size);
-	writel(dm_pci_phys_to_mem(priv->dev, (u32)(tx_desc + 1)),
+	writel(dm_pci_phys_to_mem(priv->dev, (ulong)(tx_desc + 1)),
 	       &mac_regs->tx_dsc_sw_p);
 }
 
@@ -251,7 +251,7 @@ static int pch_gbe_send(struct udevice *dev, void *packet, int length)
 	if (length < 64)
 		frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
 
-	tx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev, (u32)packet);
+	tx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev, (ulong)packet);
 	tx_desc->length = length;
 	tx_desc->tx_words_eob = length + 3;
 	tx_desc->tx_frame_ctrl = frame_ctrl;
@@ -262,7 +262,7 @@ static int pch_gbe_send(struct udevice *dev, void *packet, int length)
 	if (++priv->tx_idx >= PCH_GBE_DESC_NUM)
 		priv->tx_idx = 0;
 
-	writel(dm_pci_phys_to_mem(priv->dev, (u32)(tx_head + priv->tx_idx)),
+	writel(dm_pci_phys_to_mem(priv->dev, (ulong)(tx_head + priv->tx_idx)),
 	       &mac_regs->tx_dsc_sw_p);
 
 	start = get_timer(0);
@@ -283,7 +283,7 @@ static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp)
 	struct pch_gbe_priv *priv = dev_get_priv(dev);
 	struct pch_gbe_regs *mac_regs = priv->mac_regs;
 	struct pch_gbe_rx_desc *rx_desc;
-	u32 hw_desc, buffer_addr, length;
+	ulong hw_desc, buffer_addr, length;
 
 	rx_desc = &priv->rx_desc[priv->rx_idx];
 
@@ -291,7 +291,7 @@ static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp)
 	hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld);
 
 	/* Just return if not receiving any packet */
-	if ((u32)rx_desc == hw_desc)
+	if ((ulong)rx_desc == hw_desc)
 		return -EAGAIN;
 
 	buffer_addr = dm_pci_mem_to_phys(priv->dev, rx_desc->buffer_addr);
@@ -315,7 +315,7 @@ static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length)
 	if (++rx_swp >= PCH_GBE_DESC_NUM)
 		rx_swp = 0;
 
-	writel(dm_pci_phys_to_mem(priv->dev, (u32)(rx_head + rx_swp)),
+	writel(dm_pci_phys_to_mem(priv->dev, (ulong)(rx_head + rx_swp)),
 	       &mac_regs->rx_dsc_sw_p);
 
 	return 0;
@@ -421,7 +421,7 @@ int pch_gbe_probe(struct udevice *dev)
 {
 	struct pch_gbe_priv *priv;
 	struct eth_pdata *plat = dev_get_platdata(dev);
-	u32 iobase;
+	void *iobase;
 
 	/*
 	 * The priv structure contains the descriptors and frame buffers which
@@ -432,11 +432,9 @@ int pch_gbe_probe(struct udevice *dev)
 
 	priv->dev = dev;
 
-	dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
-	iobase &= PCI_BASE_ADDRESS_MEM_MASK;
-	iobase = dm_pci_mem_to_phys(dev, iobase);
+	iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM);
 
-	plat->iobase = iobase;
+	plat->iobase = (ulong)iobase;
 	priv->mac_regs = (struct pch_gbe_regs *)iobase;
 
 	/* Read MAC address from SROM and initialize dev->enetaddr with it */
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 7b85aa04638..d86e7a39546 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -19,6 +19,7 @@
 #include <fdtdec.h>
 #include <asm-generic/errno.h>
 #include <linux/kernel.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -154,7 +155,7 @@ static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
 	unsigned long start = get_timer(0);
 
 	while (1) {
-		val = readl(reg);
+		val = __raw_readl(reg);
 
 		if (!set)
 			val = ~val;
@@ -193,16 +194,17 @@ static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
 	if (mdio_wait(regs))
 		return 1;
 
-	u32 ctrl_reg = in_be32(&regs->mdioctrl);
-	out_be32(&regs->mdioaddr, XEL_MDIOADDR_OP_MASK |
-		 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
-	out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
+	u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
+	__raw_writel(XEL_MDIOADDR_OP_MASK
+		| ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
+		| registernum), &regs->mdioaddr);
+	__raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);
 
 	if (mdio_wait(regs))
 		return 1;
 
 	/* Read data */
-	*data = in_be32(&regs->mdiord);
+	*data = __raw_readl(&regs->mdiord);
 	return 0;
 }
 
@@ -220,11 +222,12 @@ static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
 	 * Data register. Finally, set the Status bit in the MDIO Control
 	 * register to start a MDIO write transaction.
 	 */
-	u32 ctrl_reg = in_be32(&regs->mdioctrl);
-	out_be32(&regs->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
-		 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
-	out_be32(&regs->mdiowr, data);
-	out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
+	u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
+	__raw_writel(~XEL_MDIOADDR_OP_MASK
+		& ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
+		| registernum), &regs->mdioaddr);
+	__raw_writel(data, &regs->mdiowr);
+	__raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);
 
 	if (mdio_wait(regs))
 		return 1;
@@ -327,27 +330,27 @@ static int emaclite_start(struct udevice *dev)
  * TX - TX_PING & TX_PONG initialization
  */
 	/* Restart PING TX */
-	out_be32(&regs->tx_ping_tsr, 0);
+	__raw_writel(0, &regs->tx_ping_tsr);
 	/* Copy MAC address */
 	xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_ping,
 			       ENET_ADDR_LENGTH);
 	/* Set the length */
-	out_be32(&regs->tx_ping_tplr, ENET_ADDR_LENGTH);
+	__raw_writel(ENET_ADDR_LENGTH, &regs->tx_ping_tplr);
 	/* Update the MAC address in the EMAC Lite */
-	out_be32(&regs->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
+	__raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_ping_tsr);
 	/* Wait for EMAC Lite to finish with the MAC address update */
-	while ((in_be32 (&regs->tx_ping_tsr) &
+	while ((__raw_readl(&regs->tx_ping_tsr) &
 		XEL_TSR_PROG_MAC_ADDR) != 0)
 		;
 
 	if (emaclite->txpp) {
 		/* The same operation with PONG TX */
-		out_be32(&regs->tx_pong_tsr, 0);
+		__raw_writel(0, &regs->tx_pong_tsr);
 		xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_pong,
 				       ENET_ADDR_LENGTH);
-		out_be32(&regs->tx_pong_tplr, ENET_ADDR_LENGTH);
-		out_be32(&regs->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
-		while ((in_be32(&regs->tx_pong_tsr) &
+		__raw_writel(ENET_ADDR_LENGTH, &regs->tx_pong_tplr);
+		__raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_pong_tsr);
+		while ((__raw_readl(&regs->tx_pong_tsr) &
 		       XEL_TSR_PROG_MAC_ADDR) != 0)
 			;
 	}
@@ -356,13 +359,13 @@ static int emaclite_start(struct udevice *dev)
  * RX - RX_PING & RX_PONG initialization
  */
 	/* Write out the value to flush the RX buffer */
-	out_be32(&regs->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);
+	__raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_ping_rsr);
 
 	if (emaclite->rxpp)
-		out_be32(&regs->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);
+		__raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_pong_rsr);
 
-	out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
-	if (in_be32(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
+	__raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, &regs->mdioctrl);
+	if (__raw_readl(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
 		if (!setup_phy(dev))
 			return -1;
 
@@ -379,9 +382,9 @@ static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
 	 * Read the other buffer register
 	 * and determine if the other buffer is available
 	 */
-	tmp = ~in_be32(&regs->tx_ping_tsr);
+	tmp = ~__raw_readl(&regs->tx_ping_tsr);
 	if (emaclite->txpp)
-		tmp |= ~in_be32(&regs->tx_pong_tsr);
+		tmp |= ~__raw_readl(&regs->tx_pong_tsr);
 
 	return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
 }
@@ -405,40 +408,42 @@ static int emaclite_send(struct udevice *dev, void *ptr, int len)
 	if (!maxtry) {
 		printf("Error: Timeout waiting for ethernet TX buffer\n");
 		/* Restart PING TX */
-		out_be32(&regs->tx_ping_tsr, 0);
+		__raw_writel(0, &regs->tx_ping_tsr);
 		if (emaclite->txpp) {
-			out_be32(&regs->tx_pong_tsr, 0);
+			__raw_writel(0, &regs->tx_pong_tsr);
 		}
 		return -1;
 	}
 
 	/* Determine if the expected buffer address is empty */
-	reg = in_be32(&regs->tx_ping_tsr);
+	reg = __raw_readl(&regs->tx_ping_tsr);
 	if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
 		debug("Send packet from tx_ping buffer\n");
 		/* Write the frame to the buffer */
 		xemaclite_alignedwrite(ptr, &regs->tx_ping, len);
-		out_be32(&regs->tx_ping_tplr, len &
-			(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO));
-		reg = in_be32(&regs->tx_ping_tsr);
+		__raw_writel(len
+			& (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO),
+		       &regs->tx_ping_tplr);
+		reg = __raw_readl(&regs->tx_ping_tsr);
 		reg |= XEL_TSR_XMIT_BUSY_MASK;
-		out_be32(&regs->tx_ping_tsr, reg);
+		__raw_writel(reg, &regs->tx_ping_tsr);
 		return 0;
 	}
 
 	if (emaclite->txpp) {
 		/* Determine if the expected buffer address is empty */
-		reg = in_be32(&regs->tx_pong_tsr);
+		reg = __raw_readl(&regs->tx_pong_tsr);
 		if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
 			debug("Send packet from tx_pong buffer\n");
 			/* Write the frame to the buffer */
 			xemaclite_alignedwrite(ptr, &regs->tx_pong, len);
-			out_be32(&regs->tx_pong_tplr, len &
+			__raw_writel(len &
 				 (XEL_TPLR_LENGTH_MASK_HI |
-				  XEL_TPLR_LENGTH_MASK_LO));
-			reg = in_be32(&regs->tx_pong_tsr);
+				  XEL_TPLR_LENGTH_MASK_LO),
+				  &regs->tx_pong_tplr);
+			reg = __raw_readl(&regs->tx_pong_tsr);
 			reg |= XEL_TSR_XMIT_BUSY_MASK;
-			out_be32(&regs->tx_pong_tsr, reg);
+			__raw_writel(reg, &regs->tx_pong_tsr);
 			return 0;
 		}
 	}
@@ -458,7 +463,7 @@ static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
 
 try_again:
 	if (!emaclite->use_rx_pong_buffer_next) {
-		reg = in_be32(&regs->rx_ping_rsr);
+		reg = __raw_readl(&regs->rx_ping_rsr);
 		debug("Testing data at rx_ping\n");
 		if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
 			debug("Data found in rx_ping buffer\n");
@@ -478,7 +483,7 @@ try_again:
 			goto try_again;
 		}
 	} else {
-		reg = in_be32(&regs->rx_pong_rsr);
+		reg = __raw_readl(&regs->rx_pong_rsr);
 		debug("Testing data at rx_pong\n");
 		if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
 			debug("Data found in rx_pong buffer\n");
@@ -525,9 +530,9 @@ try_again:
 				      length - first_read);
 
 	/* Acknowledge the frame */
-	reg = in_be32(ack);
+	reg = __raw_readl(ack);
 	reg &= ~XEL_RSR_RECV_DONE_MASK;
-	out_be32(ack, reg);
+	__raw_writel(reg, ack);
 
 	debug("Packet receive from 0x%p, length %dB\n", addr, length);
 	*packetp = etherrxbuff;
@@ -595,7 +600,8 @@ static int emaclite_ofdata_to_platdata(struct udevice *dev)
 	int offset = 0;
 
 	pdata->iobase = (phys_addr_t)dev_get_addr(dev);
-	emaclite->regs = (struct emaclite_regs *)pdata->iobase;
+	emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
+								 0x10000);
 
 	emaclite->phyaddr = -1;
 
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 669e37bb5dc..9a7c187446b 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -39,4 +39,11 @@ config PCI_TEGRA
 	  with a total of 5 lanes. Some boards require this for Ethernet
 	  support to work (e.g. beaver, jetson-tk1).
 
+config PCI_XILINX
+	bool "Xilinx AXI Bridge for PCI Express"
+	depends on DM_PCI
+	help
+	  Enable support for the Xilinx AXI bridge for PCI express, an IP block
+	  which can be used on some generations of Xilinx FPGAs.
+
 endmenu
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index f8be9bf1ea5..9583e91ceb0 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -31,3 +31,4 @@ obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
 obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
 obj-$(CONFIG_WINBOND_83C553) += w83c553f.o
 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
+obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 342b78c0c4b..3b00e6a41b3 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -837,7 +837,7 @@ static int pci_uclass_pre_probe(struct udevice *bus)
 	hose = bus->uclass_priv;
 
 	/* For bridges, use the top-level PCI controller */
-	if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
+	if (!device_is_on_pci_bus(bus)) {
 		hose->ctlr = bus;
 		ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
 				bus->of_offset);
diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c
new file mode 100644
index 00000000000..521600180e6
--- /dev/null
+++ b/drivers/pci/pcie_xilinx.c
@@ -0,0 +1,220 @@
+/*
+ * Xilinx AXI Bridge for PCI Express Driver
+ *
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+
+#include <asm/io.h>
+
+/**
+ * struct xilinx_pcie - Xilinx PCIe controller state
+ * @hose: The parent classes PCI controller state
+ * @cfg_base: The base address of memory mapped configuration space
+ */
+struct xilinx_pcie {
+	struct pci_controller hose;
+	void *cfg_base;
+};
+
+/* Register definitions */
+#define XILINX_PCIE_REG_PSCR		0x144
+#define XILINX_PCIE_REG_PSCR_LNKUP	BIT(11)
+
+/**
+ * pcie_xilinx_link_up() - Check whether the PCIe link is up
+ * @pcie: Pointer to the PCI controller state
+ *
+ * Checks whether the PCIe link for the given device is up or down.
+ *
+ * Return: true if the link is up, else false
+ */
+static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie)
+{
+	uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR);
+
+	return pscr & XILINX_PCIE_REG_PSCR_LNKUP;
+}
+
+/**
+ * pcie_xilinx_config_address() - Calculate the address of a config access
+ * @pcie: Pointer to the PCI controller state
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @paddress: Pointer to the pointer to write the calculates address to
+ *
+ * Calculates the address that should be accessed to perform a PCIe
+ * configuration space access for a given device identified by the PCIe
+ * controller device @pcie and the bus, device & function numbers in @bdf. If
+ * access to the device is not valid then the function will return an error
+ * code. Otherwise the address to access will be written to the pointer pointed
+ * to by @paddress.
+ *
+ * Return: 0 on success, else -ENODEV
+ */
+static int pcie_xilinx_config_address(struct xilinx_pcie *pcie, pci_dev_t bdf,
+				      uint offset, void **paddress)
+{
+	unsigned int bus = PCI_BUS(bdf);
+	unsigned int dev = PCI_DEV(bdf);
+	unsigned int func = PCI_FUNC(bdf);
+	void *addr;
+
+	if ((bus > 0) && !pcie_xilinx_link_up(pcie))
+		return -ENODEV;
+
+	/*
+	 * Busses 0 (host-PCIe bridge) & 1 (its immediate child) are
+	 * limited to a single device each.
+	 */
+	if ((bus < 2) && (dev > 0))
+		return -ENODEV;
+
+	addr = pcie->cfg_base;
+	addr += bus << 20;
+	addr += dev << 15;
+	addr += func << 12;
+	addr += offset;
+	*paddress = addr;
+
+	return 0;
+}
+
+/**
+ * pcie_xilinx_read_config() - Read from configuration space
+ * @pcie: Pointer to the PCI controller state
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @valuep: A pointer at which to store the read value
+ * @size: Indicates the size of access to perform
+ *
+ * Read a value of size @size from offset @offset within the configuration
+ * space of the device identified by the bus, device & function numbers in @bdf
+ * on the PCI bus @bus.
+ *
+ * Return: 0 on success, else -ENODEV or -EINVAL
+ */
+static int pcie_xilinx_read_config(struct udevice *bus, pci_dev_t bdf,
+				   uint offset, ulong *valuep,
+				   enum pci_size_t size)
+{
+	struct xilinx_pcie *pcie = dev_get_priv(bus);
+	void *address;
+	int err;
+
+	err = pcie_xilinx_config_address(pcie, bdf, offset, &address);
+	if (err < 0) {
+		*valuep = pci_get_ff(size);
+		return 0;
+	}
+
+	switch (size) {
+	case PCI_SIZE_8:
+		*valuep = __raw_readb(address);
+		return 0;
+	case PCI_SIZE_16:
+		*valuep = __raw_readw(address);
+		return 0;
+	case PCI_SIZE_32:
+		*valuep = __raw_readl(address);
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+/**
+ * pcie_xilinx_write_config() - Write to configuration space
+ * @pcie: Pointer to the PCI controller state
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @value: The value to write
+ * @size: Indicates the size of access to perform
+ *
+ * Write the value @value of size @size from offset @offset within the
+ * configuration space of the device identified by the bus, device & function
+ * numbers in @bdf on the PCI bus @bus.
+ *
+ * Return: 0 on success, else -ENODEV or -EINVAL
+ */
+static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf,
+				    uint offset, ulong value,
+				    enum pci_size_t size)
+{
+	struct xilinx_pcie *pcie = dev_get_priv(bus);
+	void *address;
+	int err;
+
+	err = pcie_xilinx_config_address(pcie, bdf, offset, &address);
+	if (err < 0)
+		return 0;
+
+	switch (size) {
+	case PCI_SIZE_8:
+		__raw_writeb(value, address);
+		return 0;
+	case PCI_SIZE_16:
+		__raw_writew(value, address);
+		return 0;
+	case PCI_SIZE_32:
+		__raw_writel(value, address);
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+/**
+ * pcie_xilinx_ofdata_to_platdata() - Translate from DT to device state
+ * @dev: A pointer to the device being operated on
+ *
+ * Translate relevant data from the device tree pertaining to device @dev into
+ * state that the driver will later make use of. This state is stored in the
+ * device's private data structure.
+ *
+ * Return: 0 on success, else -EINVAL
+ */
+static int pcie_xilinx_ofdata_to_platdata(struct udevice *dev)
+{
+	struct xilinx_pcie *pcie = dev_get_priv(dev);
+	struct fdt_resource reg_res;
+	DECLARE_GLOBAL_DATA_PTR;
+	int err;
+
+	err = fdt_get_resource(gd->fdt_blob, dev->of_offset, "reg",
+			       0, &reg_res);
+	if (err < 0) {
+		error("\"reg\" resource not found\n");
+		return err;
+	}
+
+	pcie->cfg_base = map_physmem(reg_res.start,
+				     fdt_resource_size(&reg_res),
+				     MAP_NOCACHE);
+
+	return 0;
+}
+
+static const struct dm_pci_ops pcie_xilinx_ops = {
+	.read_config	= pcie_xilinx_read_config,
+	.write_config	= pcie_xilinx_write_config,
+};
+
+static const struct udevice_id pcie_xilinx_ids[] = {
+	{ .compatible = "xlnx,axi-pcie-host-1.00.a" },
+	{ }
+};
+
+U_BOOT_DRIVER(pcie_xilinx) = {
+	.name			= "pcie_xilinx",
+	.id			= UCLASS_PCI,
+	.of_match		= pcie_xilinx_ids,
+	.ops			= &pcie_xilinx_ops,
+	.ofdata_to_platdata	= pcie_xilinx_ofdata_to_platdata,
+	.priv_auto_alloc_size	= sizeof(struct xilinx_pcie),
+};
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 88fca15357e..3f6ea4d2759 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <errno.h>
 #include <fdtdec.h>
@@ -352,6 +353,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 {
 	struct ns16550_platdata *plat = dev->platdata;
 	fdt_addr_t addr;
+	struct clk clk;
+	int err;
 
 	/* try Processor Local Bus device first */
 	addr = dev_get_addr(dev);
@@ -397,9 +400,21 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 				     "reg-offset", 0);
 	plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
 					 "reg-shift", 0);
-	plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
-				     "clock-frequency",
-				     CONFIG_SYS_NS16550_CLK);
+
+	err = clk_get_by_index(dev, 0, &clk);
+	if (!err) {
+		err = clk_get_rate(&clk);
+		if (!IS_ERR_VALUE(err))
+			plat->clock = err;
+	} else if (err != -ENODEV && err != -ENOSYS) {
+		debug("ns16550 failed to get clock\n");
+		return err;
+	}
+
+	if (!plat->clock)
+		plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+					     "clock-frequency",
+					     CONFIG_SYS_NS16550_CLK);
 	if (!plat->clock) {
 		debug("ns16550 clock not defined\n");
 		return -EINVAL;