diff options
| author | Simon Glass <sjg@chromium.org> | 2011-08-10 15:45:52 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2011-08-29 10:59:29 -0700 |
| commit | 83861f814d52d5a37d9420071c3e413c8b03ce3d (patch) | |
| tree | 7daa22f8b03750b8c5defe9e6d50c415812cbe06 /drivers | |
| parent | 5ef3854ce9826ec7b2d48b4dfc8cb3501108e2dd (diff) | |
tegra2: Increase SPI flash speed to 48MHz
The W25X40AVSNI SPI flash part can run at 100MHz according to Winbond's
datasheet August 7, 2009, RevF.
The Tegra20 datasheet says it's SPI peripheral can run up to 50Mbps.
The way the Tegra2 clocks are set up we can only do 48MHz.
So this commit doubles the speed from 24MHz to 48MHz.
This reduces onestop boot time by about 15ms, twostop would be more.
BUG=chromium-os:17805
TEST=build and boot on Aebl, Seaboard
Change-Id: I90dd140c5d8d71e9361cd7b881d6931cc6c0bcb3
Reviewed-on: http://gerrit.chromium.org/gerrit/5773
Reviewed-by: Tom Warren <twarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/spi/tegra2_spi.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/spi/tegra2_spi.c b/drivers/spi/tegra2_spi.c index f82e8656756..7885a347d74 100644 --- a/drivers/spi/tegra2_spi.c +++ b/drivers/spi/tegra2_spi.c @@ -79,8 +79,8 @@ void spi_init(void) struct spi_tegra *spi = (struct spi_tegra *)TEGRA2_SPI_BASE; u32 reg; - /* Change SPI clock to 24MHz, PLLP_OUT0 source */ - clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, CLK_24M); + /* Change SPI clock to 48MHz, PLLP_OUT0 source */ + clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, CLK_48M); /* Clear stale status here */ reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \ |