Merge tag 'u-boot-imx-20190101' of git://www.denx.de/git/u-boot-imx

imx for 2019.01

- introduce support for i.MX8M
- fix size limit for Vhybrid / pico boards
- several board fixes
- w1 driver for MX2x / MX5x

26 files changed, 1906 insertions, 18 deletions

diff --git a/drivers/Makefile b/drivers/Makefile
index 5e3b122769..8c53e05d2f 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
 obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
 obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
 obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
+obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
 obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
 obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
 obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
index b764add060..d4b393d25e 100644
--- a/drivers/ddr/Kconfig
+++ b/drivers/ddr/Kconfig
@@ -1 +1,2 @@
 source "drivers/ddr/altera/Kconfig"
+source "drivers/ddr/imx/Kconfig"
diff --git a/drivers/ddr/imx/Kconfig b/drivers/ddr/imx/Kconfig
new file mode 100644
index 0000000000..7e06fb2f7d
--- /dev/null
+++ b/drivers/ddr/imx/Kconfig
@@ -0,0 +1 @@
+source "drivers/ddr/imx/imx8m/Kconfig"
diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig
new file mode 100644
index 0000000000..71f466f5ec
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/Kconfig
@@ -0,0 +1,22 @@
+config IMX8M_DRAM
+	bool "imx8m dram"
+
+config IMX8M_LPDDR4
+	bool "imx8m lpddr4"
+	select IMX8M_DRAM
+	help
+	  Select the i.MX8M LPDDR4 driver support on i.MX8M SOC.
+
+config IMX8M_DDR4
+	bool "imx8m ddr4"
+	select IMX8M_DRAM
+	help
+	  Select the i.MX8M DDR4 driver support on i.MX8M SOC.
+
+config SAVED_DRAM_TIMING_BASE
+	hex "Define the base address for saved dram timing"
+	help
+	  after DRAM is trained, need to save the dram related timming
+	  info into memory for low power use. OCRAM_S is used for this
+	  purpose on i.MX8MM.
+	default 0x180000
diff --git a/drivers/ddr/imx/imx8m/Makefile b/drivers/ddr/imx/imx8m/Makefile
new file mode 100644
index 0000000000..64f9ab20e6
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o
+obj-$(CONFIG_IMX8M_DDR4) += ddr4_init.o
+endif
diff --git a/drivers/ddr/imx/imx8m/ddr4_init.c b/drivers/ddr/imx/imx8m/ddr4_init.c
new file mode 100644
index 0000000000..031cdc57e1
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/ddr4_init.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8m_ddr.h>
+#include <asm/arch/sys_proto.h>
+
+void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
+{
+	int i = 0;
+
+	for (i = 0; i < num; i++) {
+		reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
+		ddrc_cfg++;
+	}
+}
+
+void ddr_init(struct dram_timing_info *dram_timing)
+{
+	volatile unsigned int tmp_t;
+	/*
+	 * assert [0]ddr1_preset_n, [1]ddr1_core_reset_n,
+	 * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n,
+	 * [4]src_system_rst_b!
+	 */
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F);
+	/* deassert [4]src_system_rst_b! */
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
+
+	/*
+	 * change the clock source of dram_apb_clk_root
+	 * to source 4 --800MHz/4
+	 */
+	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(4) |
+			     CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
+
+	dram_pll_init(DRAM_PLL_OUT_600M);
+
+	reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
+	reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
+
+	/* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
+
+	reg32_write(DDRC_DBG1(0), 0x00000001);
+	reg32_write(DDRC_PWRCTL(0), 0x00000001);
+
+	while (0 != (0x7 & reg32_read(DDRC_STAT(0))))
+		;
+
+	/* config the uMCTL2's registers */
+	ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
+
+	reg32_write(DDRC_RFSHCTL3(0), 0x00000001);
+	/* RESET: <ctn> DEASSERTED */
+	/* RESET: <a Port 0  DEASSERTED(0) */
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
+
+	reg32_write(DDRC_DBG1(0), 0x00000000);
+	reg32_write(DDRC_PWRCTL(0), 0x00000aa);
+	reg32_write(DDRC_SWCTL(0), 0x00000000);
+
+	reg32_write(DDRC_DFIMISC(0), 0x00000000);
+
+	/* config the DDR PHY's registers */
+	ddr_cfg_phy(dram_timing);
+
+	do {
+		tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
+				   4 * 0x00020097);
+	} while (tmp_t != 0);
+
+	reg32_write(DDRC_DFIMISC(0), 0x00000020);
+
+	/* wait DFISTAT.dfi_init_complete to 1 */
+	while (0 == (0x1 & reg32_read(DDRC_DFISTAT(0))))
+		;
+
+	/* clear DFIMISC.dfi_init_complete_en */
+	reg32_write(DDRC_DFIMISC(0), 0x00000000);
+	/* set DFIMISC.dfi_init_complete_en again */
+	reg32_write(DDRC_DFIMISC(0), 0x00000001);
+	reg32_write(DDRC_PWRCTL(0), 0x0000088);
+
+	/*
+	 * set SWCTL.sw_done to enable quasi-dynamic register
+	 * programming outside reset.
+	 */
+	reg32_write(DDRC_SWCTL(0), 0x00000001);
+	/* wait SWSTAT.sw_done_ack to 1 */
+	while (0 == (0x1 & reg32_read(DDRC_SWSTAT(0))))
+		;
+
+	/* wait STAT to normal state */
+	while (0x1 != (0x7 & reg32_read(DDRC_STAT(0))))
+		;
+
+	reg32_write(DDRC_PWRCTL(0), 0x0000088);
+	reg32_write(DDRC_PCTRL_0(0), 0x00000001);
+	/* dis_auto-refresh is set to 0 */
+	reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+
+	/* save the dram timing config into memory */
+	dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
+}
diff --git a/drivers/ddr/imx/imx8m/ddrphy_csr.c b/drivers/ddr/imx/imx8m/ddrphy_csr.c
new file mode 100644
index 0000000000..67dd4e7059
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/ddrphy_csr.c
@@ -0,0 +1,732 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+uint32_t ddrphy_trained_csr_num = ARRAY_SIZE(ddrphy_trained_csr);
diff --git a/drivers/ddr/imx/imx8m/ddrphy_train.c b/drivers/ddr/imx/imx8m/ddrphy_train.c
new file mode 100644
index 0000000000..18f7ed7fea
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/ddrphy_train.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+void ddr_cfg_phy(struct dram_timing_info *dram_timing)
+{
+	struct dram_cfg_param *dram_cfg;
+	struct dram_fsp_msg *fsp_msg;
+	unsigned int num;
+	int i = 0;
+	int j = 0;
+
+	/* initialize PHY configuration */
+	dram_cfg = dram_timing->ddrphy_cfg;
+	num  = dram_timing->ddrphy_cfg_num;
+	for (i = 0; i < num; i++) {
+		/* config phy reg */
+		dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
+		dram_cfg++;
+	}
+
+	/* load the frequency setpoint message block config */
+	fsp_msg = dram_timing->fsp_msg;
+	for (i = 0; i < dram_timing->fsp_msg_num; i++) {
+		debug("DRAM PHY training for %dMTS\n", fsp_msg->drate);
+		/* set dram PHY input clocks to desired frequency */
+		ddrphy_init_set_dfi_clk(fsp_msg->drate);
+
+		/* load the dram training firmware image */
+		dwc_ddrphy_apb_wr(0xd0000, 0x0);
+		ddr_load_train_firmware(fsp_msg->fw_type);
+
+		/* load the frequency set point message block parameter */
+		dram_cfg = fsp_msg->fsp_cfg;
+		num = fsp_msg->fsp_cfg_num;
+		for (j = 0; j < num; j++) {
+			dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
+			dram_cfg++;
+		}
+
+		/*
+		 * -------------------- excute the firmware --------------------
+		 * Running the firmware is a simply process to taking the
+		 * PMU out of reset and stall, then the firwmare will be run
+		 * 1. reset the PMU;
+		 * 2. begin the excution;
+		 * 3. wait for the training done;
+		 * 4. read the message block result.
+		 * -------------------------------------------------------------
+		 */
+		dwc_ddrphy_apb_wr(0xd0000, 0x1);
+		dwc_ddrphy_apb_wr(0xd0099, 0x9);
+		dwc_ddrphy_apb_wr(0xd0099, 0x1);
+		dwc_ddrphy_apb_wr(0xd0099, 0x0);
+
+		/* Wait for the training firmware to complete */
+		wait_ddrphy_training_complete();
+
+		/* Halt the microcontroller. */
+		dwc_ddrphy_apb_wr(0xd0099, 0x1);
+
+		/* Read the Message Block results */
+		dwc_ddrphy_apb_wr(0xd0000, 0x0);
+		ddrphy_init_read_msg_block(fsp_msg->fw_type);
+		dwc_ddrphy_apb_wr(0xd0000, 0x1);
+
+		fsp_msg++;
+	}
+
+	/* Load PHY Init Engine Image */
+	dram_cfg = dram_timing->ddrphy_pie;
+	num = dram_timing->ddrphy_pie_num;
+	for (i = 0; i < num; i++) {
+		dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
+		dram_cfg++;
+	}
+
+	/* save the ddr PHY trained CSR in memory for low power use */
+	ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num);
+}
diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c
new file mode 100644
index 0000000000..4732539764
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+* Copyright 2018 NXP
+*/
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static inline void poll_pmu_message_ready(void)
+{
+	unsigned int reg;
+
+	do {
+		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
+	} while (reg & 0x1);
+}
+
+static inline void ack_pmu_message_receive(void)
+{
+	unsigned int reg;
+
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0);
+
+	do {
+		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
+	} while (!(reg & 0x1));
+
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1);
+}
+
+static inline unsigned int get_mail(void)
+{
+	unsigned int reg;
+
+	poll_pmu_message_ready();
+
+	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
+
+	ack_pmu_message_receive();
+
+	return reg;
+}
+
+static inline unsigned int get_stream_message(void)
+{
+	unsigned int reg, reg2;
+
+	poll_pmu_message_ready();
+
+	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
+
+	reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034);
+
+	reg2 = (reg2 << 16) | reg;
+
+	ack_pmu_message_receive();
+
+	return reg2;
+}
+
+static inline void decode_major_message(unsigned int mail)
+{
+	debug("[PMU Major message = 0x%08x]\n", mail);
+}
+
+static inline void decode_streaming_message(void)
+{
+	unsigned int string_index, arg __maybe_unused;
+	int i = 0;
+
+	string_index = get_stream_message();
+	debug("PMU String index = 0x%08x\n", string_index);
+	while (i < (string_index & 0xffff)) {
+		arg = get_stream_message();
+		debug("arg[%d] = 0x%08x\n", i, arg);
+		i++;
+	}
+
+	debug("\n");
+}
+
+void wait_ddrphy_training_complete(void)
+{
+	unsigned int mail;
+
+	while (1) {
+		mail = get_mail();
+		decode_major_message(mail);
+		if (mail == 0x08) {
+			decode_streaming_message();
+		} else if (mail == 0x07) {
+			debug("Training PASS\n");
+			break;
+		} else if (mail == 0xff) {
+			printf("Training FAILED\n");
+			break;
+		}
+	}
+}
+
+void ddrphy_init_set_dfi_clk(unsigned int drate)
+{
+	switch (drate) {
+	case 3200:
+		dram_pll_init(MHZ(800));
+		dram_disable_bypass();
+		break;
+	case 3000:
+		dram_pll_init(MHZ(750));
+		dram_disable_bypass();
+		break;
+	case 2400:
+		dram_pll_init(MHZ(600));
+		dram_disable_bypass();
+		break;
+	case 1600:
+		dram_pll_init(MHZ(400));
+		dram_disable_bypass();
+		break;
+	case 667:
+		dram_pll_init(MHZ(167));
+		dram_disable_bypass();
+		break;
+	case 400:
+		dram_enable_bypass(MHZ(400));
+		break;
+	case 100:
+		dram_enable_bypass(MHZ(100));
+		break;
+	default:
+		return;
+	}
+}
+
+void ddrphy_init_read_msg_block(enum fw_type type)
+{
+}
+
+void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr,
+		     unsigned int mr_data)
+{
+	unsigned int tmp;
+	/*
+	 * 1. Poll MRSTAT.mr_wr_busy until it is 0.
+	 * This checks that there is no outstanding MR transaction.
+	 * No writes should be performed to MRCTRL0 and MRCTRL1 if
+	 * MRSTAT.mr_wr_busy = 1.
+	 */
+	do {
+		tmp = reg32_read(DDRC_MRSTAT(0));
+	} while (tmp & 0x1);
+	/*
+	 * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and
+	 * (for MRWs) MRCTRL1.mr_data to define the MR transaction.
+	 */
+	reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4));
+	reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data);
+	reg32setbit(DDRC_MRCTRL0(0), 31);
+}
+
+unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
+{
+	unsigned int tmp;
+
+	reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
+	do {
+		tmp = reg32_read(DDRC_MRSTAT(0));
+	} while (tmp & 0x1);
+
+	reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
+	reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
+	reg32setbit(DDRC_MRCTRL0(0), 31);
+	do {
+		tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
+	} while ((tmp & 0x8) == 0);
+	tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
+	tmp = tmp & 0xff;
+	reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
+
+	return tmp;
+}
diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/imx8m/helper.c
new file mode 100644
index 0000000000..61cd4f6db1
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/helper.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMEM_LEN 32768 /* byte */
+#define DMEM_LEN 16384 /* byte */
+#define IMEM_2D_OFFSET	49152
+
+#define IMEM_OFFSET_ADDR 0x00050000
+#define DMEM_OFFSET_ADDR 0x00054000
+#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
+
+/* We need PHY iMEM PHY is 32KB padded */
+void ddr_load_train_firmware(enum fw_type type)
+{
+	u32 tmp32, i;
+	u32 error = 0;
+	unsigned long pr_to32, pr_from32;
+	unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
+	unsigned long imem_start = (unsigned long)&_end + fw_offset;
+	unsigned long dmem_start = imem_start + IMEM_LEN;
+
+	pr_from32 = imem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+	for (i = 0x0; i < IMEM_LEN; ) {
+		tmp32 = readl(pr_from32);
+		writew(tmp32 & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		pr_from32 += 4;
+		i += 4;
+	}
+
+	pr_from32 = dmem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+	for (i = 0x0; i < DMEM_LEN; ) {
+		tmp32 = readl(pr_from32);
+		writew(tmp32 & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		pr_from32 += 4;
+		i += 4;
+	}
+
+	debug("check ddr4_pmu_train_imem code\n");
+	pr_from32 = imem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+	for (i = 0x0; i < IMEM_LEN; ) {
+		tmp32 = (readw(pr_to32) & 0x0000ffff);
+		pr_to32 += 4;
+		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+
+		if (tmp32 != readl(pr_from32)) {
+			debug("%lx %lx\n", pr_from32, pr_to32);
+			error++;
+		}
+		pr_from32 += 4;
+		pr_to32 += 4;
+		i += 4;
+	}
+	if (error)
+		printf("check ddr4_pmu_train_imem code fail=%d\n", error);
+	else
+		debug("check ddr4_pmu_train_imem code pass\n");
+
+	debug("check ddr4_pmu_train_dmem code\n");
+	pr_from32 = dmem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+	for (i = 0x0; i < DMEM_LEN;) {
+		tmp32 = (readw(pr_to32) & 0x0000ffff);
+		pr_to32 += 4;
+		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+		if (tmp32 != readl(pr_from32)) {
+			debug("%lx %lx\n", pr_from32, pr_to32);
+			error++;
+		}
+		pr_from32 += 4;
+		pr_to32 += 4;
+		i += 4;
+	}
+
+	if (error)
+		printf("check ddr4_pmu_train_dmem code fail=%d", error);
+	else
+		debug("check ddr4_pmu_train_dmem code pass\n");
+}
+
+void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr,
+			     unsigned int num)
+{
+	int i = 0;
+
+	/* enable the ddrphy apb */
+	dwc_ddrphy_apb_wr(0xd0000, 0x0);
+	dwc_ddrphy_apb_wr(0xc0080, 0x3);
+	for (i = 0; i < num; i++) {
+		ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg);
+		ddrphy_csr++;
+	}
+	/* disable the ddrphy apb */
+	dwc_ddrphy_apb_wr(0xc0080, 0x2);
+	dwc_ddrphy_apb_wr(0xd0000, 0x1);
+}
+
+void dram_config_save(struct dram_timing_info *timing_info,
+		      unsigned long saved_timing_base)
+{
+	int i = 0;
+	struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base;
+	struct dram_cfg_param *cfg;
+
+	saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num;
+	saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num;
+	saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num;
+	saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num;
+
+	/* save the fsp table */
+	for (i = 0; i < 4; i++)
+		saved_timing->fsp_table[i] = timing_info->fsp_table[i];
+
+	cfg = (struct dram_cfg_param *)(saved_timing_base +
+					sizeof(*timing_info));
+
+	/* save ddrc config */
+	saved_timing->ddrc_cfg = cfg;
+	for (i = 0; i < timing_info->ddrc_cfg_num; i++) {
+		cfg->reg = timing_info->ddrc_cfg[i].reg;
+		cfg->val = timing_info->ddrc_cfg[i].val;
+		cfg++;
+	}
+
+	/* save ddrphy config */
+	saved_timing->ddrphy_cfg = cfg;
+	for (i = 0; i < timing_info->ddrphy_cfg_num; i++) {
+		cfg->reg = timing_info->ddrphy_cfg[i].reg;
+		cfg->val = timing_info->ddrphy_cfg[i].val;
+		cfg++;
+	}
+
+	/* save the ddrphy csr */
+	saved_timing->ddrphy_trained_csr = cfg;
+	for (i = 0; i < ddrphy_trained_csr_num; i++) {
+		cfg->reg = ddrphy_trained_csr[i].reg;
+		cfg->val = ddrphy_trained_csr[i].val;
+		cfg++;
+	}
+
+	/* save the ddrphy pie */
+	saved_timing->ddrphy_pie = cfg;
+	for (i = 0; i < timing_info->ddrphy_pie_num; i++) {
+		cfg->reg = timing_info->ddrphy_pie[i].reg;
+		cfg->val = timing_info->ddrphy_pie[i].val;
+		cfg++;
+	}
+}
diff --git a/drivers/ddr/imx/imx8m/lpddr4_init.c b/drivers/ddr/imx/imx8m/lpddr4_init.c
new file mode 100644
index 0000000000..a4bc1de8eb
--- /dev/null
+++ b/drivers/ddr/imx/imx8m/lpddr4_init.c
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+* Copyright 2018 NXP
+*
+*/
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+#include <asm/arch/sys_proto.h>
+
+void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
+{
+	int i = 0;
+
+	for (i = 0; i < num; i++) {
+		reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
+		ddrc_cfg++;
+	}
+}
+
+void ddr_init(struct dram_timing_info *dram_timing)
+{
+	unsigned int tmp;
+
+	debug("DDRINFO: start lpddr4 ddr init\n");
+	/* step 1: reset */
+	if (is_imx8mq()) {
+		reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F);
+		reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
+		reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
+	} else {
+		reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F);
+		reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
+	}
+
+	mdelay(100);
+
+	debug("DDRINFO: reset done\n");
+	/*
+	 * change the clock source of dram_apb_clk_root:
+	 * source 4 800MHz /4 = 200MHz
+	 */
+	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(4) |
+			     CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
+
+	/* disable iso */
+	reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
+	reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
+
+	debug("DDRINFO: cfg clk\n");
+	dram_pll_init(MHZ(750));
+
+	/*
+	 * release [0]ddr1_preset_n, [1]ddr1_core_reset_n,
+	 * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n
+	 */
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
+
+	/*step2 Configure uMCTL2's registers */
+	debug("DDRINFO: ddrc config start\n");
+	lpddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
+	debug("DDRINFO: ddrc config done\n");
+
+	/*
+	 * step3 de-assert all reset
+	 * RESET: <core_ddrc_rstn> DEASSERTED
+	 * RESET: <aresetn> for Port 0  DEASSERT(0)ED
+	 */
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
+
+	reg32_write(DDRC_DBG1(0), 0x00000000);
+	/* step4 */
+	/* [0]dis_auto_refresh=1 */
+	reg32_write(DDRC_RFSHCTL3(0), 0x00000011);
+
+	/* [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR */
+	reg32_write(DDRC_PWRCTL(0), 0x000000a8);
+
+	do {
+		tmp = reg32_read(DDRC_STAT(0));
+	} while ((tmp & 0x33f) != 0x223);
+
+	reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */
+
+	/* step5 */
+	reg32_write(DDRC_SWCTL(0), 0x00000000);
+
+	/* step6 */
+	tmp = reg32_read(DDRC_MSTR2(0));
+	if (tmp == 0x2)
+		reg32_write(DDRC_DFIMISC(0), 0x00000210);
+	else if (tmp == 0x1)
+		reg32_write(DDRC_DFIMISC(0), 0x00000110);
+	else
+		reg32_write(DDRC_DFIMISC(0), 0x00000010);
+
+	/* step7 [0]--1: disable quasi-dynamic programming */
+	reg32_write(DDRC_SWCTL(0), 0x00000001);
+
+	/* step8 Configure LPDDR4 PHY's registers */
+	debug("DDRINFO:ddrphy config start\n");
+	ddr_cfg_phy(dram_timing);
+	debug("DDRINFO: ddrphy config done\n");
+
+	/*
+	 * step14 CalBusy.0 =1, indicates the calibrator is actively
+	 * calibrating. Wait Calibrating done.
+	 */
+	do {
+		tmp = reg32_read(DDRPHY_CalBusy(0));
+	} while ((tmp & 0x1));
+
+	debug("DDRINFO:ddrphy calibration done\n");
+
+	/* step15 [0]--0: to enable quasi-dynamic programming */
+	reg32_write(DDRC_SWCTL(0), 0x00000000);
+
+	/* step16 */
+	tmp = reg32_read(DDRC_MSTR2(0));
+	if (tmp == 0x2)
+		reg32_write(DDRC_DFIMISC(0), 0x00000230);
+	else if (tmp == 0x1)
+		reg32_write(DDRC_DFIMISC(0), 0x00000130);
+	else
+		reg32_write(DDRC_DFIMISC(0), 0x00000030);
+
+	/* step17 [0]--1: disable quasi-dynamic programming */
+	reg32_write(DDRC_SWCTL(0), 0x00000001);
+	/* step18 wait DFISTAT.dfi_init_complete to 1 */
+	do {
+		tmp = reg32_read(DDRC_DFISTAT(0));
+	} while ((tmp & 0x1) == 0x0);
+
+	/* step19 */
+	reg32_write(DDRC_SWCTL(0), 0x00000000);
+
+	/* step20~22 */
+	tmp = reg32_read(DDRC_MSTR2(0));
+	if (tmp == 0x2) {
+		reg32_write(DDRC_DFIMISC(0), 0x00000210);
+		/* set DFIMISC.dfi_init_complete_en again */
+		reg32_write(DDRC_DFIMISC(0), 0x00000211);
+	} else if (tmp == 0x1) {
+		reg32_write(DDRC_DFIMISC(0), 0x00000110);
+		/* set DFIMISC.dfi_init_complete_en again */
+		reg32_write(DDRC_DFIMISC(0), 0x00000111);
+	} else {
+		/* clear DFIMISC.dfi_init_complete_en */
+		reg32_write(DDRC_DFIMISC(0), 0x00000010);
+		/* set DFIMISC.dfi_init_complete_en again */
+		reg32_write(DDRC_DFIMISC(0), 0x00000011);
+	}
+
+	/* step23 [5]selfref_sw=0; */
+	reg32_write(DDRC_PWRCTL(0), 0x00000008);
+	/* step24 sw_done=1 */
+	reg32_write(DDRC_SWCTL(0), 0x00000001);
+
+	/* step25 wait SWSTAT.sw_done_ack to 1 */
+	do {
+		tmp = reg32_read(DDRC_SWSTAT(0));
+	} while ((tmp & 0x1) == 0x0);
+
+#ifdef DFI_BUG_WR
+	reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001);
+#endif
+	/* wait STAT.operating_mode([1:0] for ddr3) to normal state */
+	do {
+		tmp = reg32_read(DDRC_STAT(0));
+	} while ((tmp & 0x3) != 0x1);
+
+	/* step26 */
+	reg32_write(DDRC_RFSHCTL3(0), 0x00000010);
+
+	/* enable port 0 */
+	reg32_write(DDRC_PCTRL_0(0), 0x00000001);
+	debug("DDRINFO: ddrmix config done\n");
+
+	/* save the dram timing config into memory */
+	dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
+}
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index b820160ae7..8bd30c75b2 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -40,15 +40,15 @@ static unsigned long gpio_ports[] = {
 	[2] = GPIO3_BASE_ADDR,
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-		defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \
+		defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
 		defined(CONFIG_ARCH_IMX8)
 	[3] = GPIO4_BASE_ADDR,
 #endif
 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-		defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \
+		defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
 		defined(CONFIG_ARCH_IMX8)
 	[4] = GPIO5_BASE_ADDR,
-#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M))
+#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_IMX8M))
 	[5] = GPIO6_BASE_ADDR,
 #endif
 #endif
@@ -353,13 +353,13 @@ static const struct mxc_gpio_plat mxc_plat[] = {
 	{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-		defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
+		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
 #endif
 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-		defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
+		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
-#ifndef CONFIG_MX8M
+#ifndef CONFIG_IMX8M
 	{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
 #endif
 #endif
@@ -377,13 +377,13 @@ U_BOOT_DEVICES(mxc_gpios) = {
 	{ "gpio_mxc", &mxc_plat[2] },
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-		defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
+		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ "gpio_mxc", &mxc_plat[3] },
 #endif
 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-		defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
+		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ "gpio_mxc", &mxc_plat[4] },
-#ifndef CONFIG_MX8M
+#ifndef CONFIG_IMX8M
 	{ "gpio_mxc", &mxc_plat[5] },
 #endif
 #endif
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 9ff475d925..f84fe88db1 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -34,7 +34,7 @@
 #define BM_OUT_STATUS_DED				0x00000400
 #define BM_OUT_STATUS_LOCKED			0x00000800
 #define BM_OUT_STATUS_PROGFAIL			0x00001000
-#elif defined(CONFIG_MX8M)
+#elif defined(CONFIG_IMX8M)
 #define BM_CTRL_ADDR			0x000000ff
 #else
 #define BM_CTRL_ADDR			0x0000007f
@@ -80,7 +80,7 @@
 #elif defined(CONFIG_MX7ULP)
 #define FUSE_BANK_SIZE	0x80
 #define FUSE_BANKS	31
-#elif defined(CONFIG_MX8M)
+#elif defined(CONFIG_IMX8M)
 #define FUSE_BANK_SIZE	0x40
 #define FUSE_BANKS	64
 #else
@@ -298,7 +298,7 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
 	u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
 #ifdef CONFIG_MX7
 	u32 addr = bank;
-#elif defined CONFIG_MX8M
+#elif defined CONFIG_IMX8M
 	u32 addr = bank << 2 | word;
 #else
 	u32 addr;
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 3cdfa7f5a6..74007e2ad4 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -259,7 +259,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 	int timeout;
 	struct fsl_esdhc *regs = priv->esdhc_regs;
 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
-	defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
 	dma_addr_t addr;
 #endif
 	uint wml_value;
@@ -273,7 +273,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
-	defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
 		addr = virt_to_phys((void *)(data->dest));
 		if (upper_32_bits(addr))
 			printf("Error found for upper 32 bits\n");
@@ -303,7 +303,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 					wml_value << 16);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
-	defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
 		addr = virt_to_phys((void *)(data->src));
 		if (upper_32_bits(addr))
 			printf("Error found for upper 32 bits\n");
@@ -369,7 +369,7 @@ static void check_and_invalidate_dcache_range
 	unsigned size = roundup(ARCH_DMA_MINALIGN,
 				data->blocks*data->blocksize);
 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
-	defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
 	dma_addr_t addr;
 
 	addr = virt_to_phys((void *)(data->dest));
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 008f7b4b4b..fd1723feda 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -88,6 +88,15 @@ config NAND_VF610_NFC
 	  The driver supports a maximum 2k page size. The driver
 	  currently does not support hardware ECC.
 
+if NAND_VF610_NFC
+
+config NAND_VF610_NFC_DT
+        bool "Support Vybrid's vf610 NAND controller as a DT device"
+        depends on OF_CONTROL && MTD
+        help
+          Enable the driver for Vybrid's vf610 NAND flash on platforms
+	  using device tree.
+
 choice
 	prompt "Hardware ECC strength"
 	depends on NAND_VF610_NFC
@@ -103,6 +112,8 @@ config SYS_NAND_VF610_NFC_60_ECC_BYTES
 
 endchoice
 
+endif
+
 config NAND_PXA3XX
 	bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
 	select SYS_NAND_SELF_INIT
diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c
index 619d0403e9..3326c2b096 100644
--- a/drivers/mtd/nand/raw/vf610_nfc.c
+++ b/drivers/mtd/nand/raw/vf610_nfc.c
@@ -31,6 +31,11 @@
 #include <nand.h>
 #include <errno.h>
 #include <asm/io.h>
+#if CONFIG_NAND_VF610_NFC_DT
+#include <dm.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#endif
 
 /* Register Offsets */
 #define NFC_FLASH_CMD1			0x3F00
@@ -641,7 +646,7 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
 		.flash_bbt = 1,
 	};
 
-	nfc = malloc(sizeof(*nfc));
+	nfc = calloc(1, sizeof(*nfc));
 	if (!nfc) {
 		printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
 		return -ENOMEM;
@@ -760,9 +765,51 @@ error:
 	return err;
 }
 
+#if CONFIG_NAND_VF610_NFC_DT
+static const struct udevice_id vf610_nfc_dt_ids[] = {
+	{
+		.compatible = "fsl,vf610-nfc",
+	},
+	{ /* sentinel */ }
+};
+
+static int vf610_nfc_dt_probe(struct udevice *dev)
+{
+	struct resource res;
+	int ret;
+
+	ret = dev_read_resource(dev, 0, &res);
+	if (ret)
+		return ret;
+
+	return vf610_nfc_nand_init(0, devm_ioremap(dev, res.start,
+						   resource_size(&res)));
+}
+
+U_BOOT_DRIVER(vf610_nfc_dt) = {
+	.name = "vf610-nfc-dt",
+	.id = UCLASS_MTD,
+	.of_match = vf610_nfc_dt_ids,
+	.probe = vf610_nfc_dt_probe,
+};
+
+void board_nand_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_MTD,
+					  DM_GET_DRIVER(vf610_nfc_dt),
+					  &dev);
+	if (ret && ret != -ENODEV)
+		pr_err("Failed to initialize NAND controller. (error %d)\n",
+		       ret);
+}
+#else
 void board_nand_init(void)
 {
 	int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
 	if (err)
 		printf("VF610 NAND init failed (err %d)\n", err);
 }
+#endif /* CONFIG_NAND_VF610_NFC_DT */
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 99c5c649a0..32fb34b793 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -604,7 +604,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
 	writel(0x00000000, &fec->eth->gaddr2);
 
 	/* Do not access reserved register */
-	if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
+	if (!is_mx6ul() && !is_mx6ull() && !is_imx8m()) {
 		/* clear MIB RAM */
 		for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
 			writel(0, i);
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index 799d1d2465..f1d5a5c50d 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -74,3 +74,17 @@ config PINCTRL_IMX8
 	  is different from the linux one, this is a simple implementation,
 	  only parses the 'fsl,pins' property and configures related
 	  registers.
+
+config PINCTRL_VYBRID
+	bool "Vybrid (vf610) pinctrl driver"
+	depends on ARCH_VF610 && PINCTRL_FULL
+	select DEVRES
+	select PINCTRL_IMX
+	help
+	  Say Y here to enable the Vybrid (vf610) pinctrl driver
+
+	  This provides a simple pinctrl driver for Vybrid SoC familiy,
+	  vf610. This feature depends on device tree
+	  configuration. This driver is different from the linux one,
+	  this is a simple implementation, only parses the 'fsl,pins'
+	  property and configure related registers.
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index 310b3b3a2e..891ee6e477 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_IMX7)		+= pinctrl-imx7.o
 obj-$(CONFIG_PINCTRL_IMX7ULP)		+= pinctrl-imx7ulp.o
 obj-$(CONFIG_PINCTRL_IMX_SCU)		+= pinctrl-scu.o
 obj-$(CONFIG_PINCTRL_IMX8)		+= pinctrl-imx8.o
+obj-$(CONFIG_PINCTRL_VYBRID)		+= pinctrl-vf610.o
diff --git a/drivers/pinctrl/nxp/pinctrl-vf610.c b/drivers/pinctrl/nxp/pinctrl-vf610.c
new file mode 100644
index 0000000000..e795b5fd8a
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-vf610.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+static struct imx_pinctrl_soc_info vf610_pinctrl_soc_info = {
+	.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
+};
+
+static int vf610_pinctrl_probe(struct udevice *dev)
+{
+	struct imx_pinctrl_soc_info *info =
+		(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+	return imx_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id vf610_pinctrl_match[] = {
+	{ .compatible = "fsl,vf610-iomuxc",
+	  .data = (ulong)&vf610_pinctrl_soc_info },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(vf610_pinctrl) = {
+	.name = "vf610-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(vf610_pinctrl_match),
+	.probe = vf610_pinctrl_probe,
+	.remove = imx_pinctrl_remove,
+	.priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+	.ops = &imx_pinctrl_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/w1/Kconfig b/drivers/w1/Kconfig
index d6e045739d..031bab25ae 100644
--- a/drivers/w1/Kconfig
+++ b/drivers/w1/Kconfig
@@ -20,6 +20,20 @@ config W1_GPIO
 	help
 	  Emulate a 1-wire bus using a GPIO.
 
+config W1_MXC
+	bool "Enable 1-wire controller on i.MX processors"
+	default no
+	depends on ARCH_MX25 || ARCH_MX31 || ARCH_MX5
+	help
+	  Support the one wire controller found in some members of the NXP
+	  i.MX SoC family.
+	  There are currently two silicon variants:
+	  V1: i.MX21, i.MX27, i.MX31, i.MX51
+	  V2: i.MX25, i.MX35, i.MX50, i.MX53
+	  Newer i.MX SoCs such as the i.MX6 do not have one wire controllers.
+
+	  The driver supports both silicon variants.
+
 endif
 
 endmenu
diff --git a/drivers/w1/Makefile b/drivers/w1/Makefile
index 7fd8697f84..9825187b65 100644
--- a/drivers/w1/Makefile
+++ b/drivers/w1/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_W1) += w1-uclass.o
 
 obj-$(CONFIG_W1_GPIO) += w1-gpio.o
+obj-$(CONFIG_W1_MXC) += mxc_w1.o
diff --git a/drivers/w1/mxc_w1.c b/drivers/w1/mxc_w1.c
new file mode 100644
index 0000000000..9279ba32b8
--- /dev/null
+++ b/drivers/w1/mxc_w1.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for one wire controller in some i.MX Socs
+ *
+ * There are currently two silicon variants:
+ * V1: i.MX21, i.MX27, i.MX31, i.MX51
+ * V2: i.MX25, i.MX35, i.MX50, i.MX53
+ * Newer i.MX SoCs such as the i.MX6 do not have one wire controllers.
+ *
+ * The V1 controller only supports single bit operations.
+ * The V2 controller is backwards compatible on the register level but adds
+ * byte size operations and a "search ROM accelerator mode"
+ *
+ * This driver does not currently support the search ROM accelerator
+ *
+ * Copyright (c) 2018 Flowbird
+ * Martin Fuzzey <martin.fuzzey@flowbird.group>
+ */
+
+#include <asm/arch/clock.h>
+#include <common.h>
+#include <dm.h>
+#include <linux/io.h>
+#include <w1.h>
+
+struct mxc_w1_regs {
+	u16 control;
+#define MXC_W1_CONTROL_RPP	BIT(7)
+#define MXC_W1_CONTROL_PST	BIT(6)
+#define MXC_W1_CONTROL_WR(x)	BIT(5 - (x))
+#define MXC_W1_CONTROL_RDST	BIT(3)
+
+	u16 time_divider;
+	u16 reset;
+
+	/* Registers below on V2 silicon only */
+	u16 command;
+	u16 tx_rx;
+	u16 interrupt;
+#define MXC_W1_INTERRUPT_TBE	BIT(2)
+#define MXC_W1_INTERRUPT_TSRE	BIT(3)
+#define MXC_W1_INTERRUPT_RBF	BIT(4)
+#define MXC_W1_INTERRUPT_RSRF	BIT(5)
+
+	u16 interrupt_en;
+};
+
+struct mxc_w1_pdata {
+	struct mxc_w1_regs *regs;
+};
+
+/*
+ * this is the low level routine to read/write a bit on the One Wire
+ * interface on the hardware. It does write 0 if parameter bit is set
+ * to 0, otherwise a write 1/read.
+ */
+static u8 mxc_w1_touch_bit(struct mxc_w1_pdata *pdata, u8 bit)
+{
+	u16 *ctrl_addr = &pdata->regs->control;
+	u16 mask = MXC_W1_CONTROL_WR(bit);
+	unsigned int timeout_cnt = 400; /* Takes max. 120us according to
+					 * datasheet.
+					 */
+
+	writew(mask, ctrl_addr);
+
+	while (timeout_cnt--) {
+		if (!(readw(ctrl_addr) & mask))
+			break;
+
+		udelay(1);
+	}
+
+	return (readw(ctrl_addr) & MXC_W1_CONTROL_RDST) ? 1 : 0;
+}
+
+static u8 mxc_w1_read_byte(struct udevice *dev)
+{
+	struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+	struct mxc_w1_regs *regs = pdata->regs;
+	u16 status;
+
+	if (dev_get_driver_data(dev) < 2) {
+		int i;
+		u8 ret = 0;
+
+		for (i = 0; i < 8; i++)
+			ret |= (mxc_w1_touch_bit(pdata, 1) << i);
+
+		return ret;
+	}
+
+	readw(&regs->tx_rx);
+	writew(0xFF, &regs->tx_rx);
+
+	do {
+		udelay(1); /* Without this bytes are sometimes duplicated... */
+		status = readw(&regs->interrupt);
+	} while (!(status & MXC_W1_INTERRUPT_RBF));
+
+	return (u8)readw(&regs->tx_rx);
+}
+
+static void mxc_w1_write_byte(struct udevice *dev, u8 byte)
+{
+	struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+	struct mxc_w1_regs *regs = pdata->regs;
+	u16 status;
+
+	if (dev_get_driver_data(dev) < 2) {
+		int i;
+
+		for (i = 0; i < 8; i++)
+			mxc_w1_touch_bit(pdata, (byte >> i) & 0x1);
+
+		return;
+	}
+
+	readw(&regs->tx_rx);
+	writew(byte, &regs->tx_rx);
+
+	do {
+		udelay(1);
+		status = readw(&regs->interrupt);
+	} while (!(status & MXC_W1_INTERRUPT_TSRE));
+}
+
+static bool mxc_w1_reset(struct udevice *dev)
+{
+	struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+	u16 reg_val;
+
+	writew(MXC_W1_CONTROL_RPP, &pdata->regs->control);
+
+	do {
+		reg_val = readw(&pdata->regs->control);
+	}  while (reg_val & MXC_W1_CONTROL_RPP);
+
+	return !(reg_val & MXC_W1_CONTROL_PST);
+}
+
+static u8 mxc_w1_triplet(struct udevice *dev, bool bdir)
+{
+	struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+	u8 id_bit   = mxc_w1_touch_bit(pdata, 1);
+	u8 comp_bit = mxc_w1_touch_bit(pdata, 1);
+	u8 retval;
+
+	if (id_bit && comp_bit)
+		return 0x03;  /* error */
+
+	if (!id_bit && !comp_bit) {
+		/* Both bits are valid, take the direction given */
+		retval = bdir ? 0x04 : 0;
+	} else {
+		/* Only one bit is valid, take that direction */
+		bdir = id_bit;
+		retval = id_bit ? 0x05 : 0x02;
+	}
+
+	mxc_w1_touch_bit(pdata, bdir);
+
+	return retval;
+}
+
+static int mxc_w1_ofdata_to_platdata(struct udevice *dev)
+{
+	struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+	fdt_addr_t addr;
+
+	addr = devfdt_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	pdata->regs = (struct mxc_w1_regs *)addr;
+
+	return 0;
+};
+
+static int mxc_w1_probe(struct udevice *dev)
+{
+	struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+	unsigned int clkrate = mxc_get_clock(MXC_IPG_PERCLK);
+	unsigned int clkdiv;
+
+	if (clkrate < 10000000) {
+		dev_err(dev, "input clock frequency (%u Hz) too low\n",
+			clkrate);
+		return -EINVAL;
+	}
+
+	clkdiv = clkrate / 1000000;
+	clkrate /= clkdiv;
+	if (clkrate < 980000 || clkrate > 1020000) {
+		dev_err(dev, "Incorrect time base frequency %u Hz\n", clkrate);
+		return -EINVAL;
+	}
+
+	writew(clkdiv - 1, &pdata->regs->time_divider);
+
+	return 0;
+}
+
+static const struct w1_ops mxc_w1_ops = {
+	.read_byte	= mxc_w1_read_byte,
+	.reset		= mxc_w1_reset,
+	.triplet	= mxc_w1_triplet,
+	.write_byte	= mxc_w1_write_byte,
+};
+
+static const struct udevice_id mxc_w1_id[] = {
+	{ .compatible = "fsl,imx21-owire", .data = 1 },
+	{ .compatible = "fsl,imx27-owire", .data = 1 },
+	{ .compatible = "fsl,imx31-owire", .data = 1 },
+	{ .compatible = "fsl,imx51-owire", .data = 1 },
+
+	{ .compatible = "fsl,imx25-owire", .data = 2 },
+	{ .compatible = "fsl,imx35-owire", .data = 2 },
+	{ .compatible = "fsl,imx50-owire", .data = 2 },
+	{ .compatible = "fsl,imx53-owire", .data = 2 },
+	{ },
+};
+
+U_BOOT_DRIVER(mxc_w1_drv) = {
+	.id				= UCLASS_W1,
+	.name				= "mxc_w1_drv",
+	.of_match			= mxc_w1_id,
+	.ofdata_to_platdata		= mxc_w1_ofdata_to_platdata,
+	.ops				= &mxc_w1_ops,
+	.platdata_auto_alloc_size	= sizeof(struct mxc_w1_pdata),
+	.probe				= mxc_w1_probe,
+};
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index b6974ad619..10fd3039aa 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -11,6 +11,12 @@ config WATCHDOG
 config HW_WATCHDOG
 	bool
 
+config WATCHDOG_RESET_DISABLE
+	bool "Disable reset watchdog"
+	help
+	   Disable reset watchdog, which can let WATCHDOG_RESET invalid, so
+	   that the watchdog will not be fed in u-boot.
+
 config BCM2835_WDT
 	bool "Enable BCM2835/2836 watchdog driver"
 	select HW_WATCHDOG
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 74738eeaf7..d901240ad1 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -7,6 +7,8 @@ obj-$(CONFIG_WDT_AT91) += at91sam9_wdt.o
 obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
 ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 vf610))
 obj-y += imx_watchdog.o
+else
+obj-$(CONFIG_IMX_WATCHDOG) += imx_watchdog.o
 endif
 obj-$(CONFIG_S5P)               += s5p_wdt.o
 obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 3f826d10eb..14cc618074 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -8,15 +8,20 @@
 #include <asm/io.h>
 #include <watchdog.h>
 #include <asm/arch/imx-regs.h>
+#ifdef CONFIG_FSL_LSCH2
+#include <asm/arch/immap_lsch2.h>
+#endif
 #include <fsl_wdog.h>
 
 #ifdef CONFIG_IMX_WATCHDOG
 void hw_watchdog_reset(void)
 {
+#ifndef CONFIG_WATCHDOG_RESET_DISABLE
 	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 
 	writew(0x5555, &wdog->wsr);
 	writew(0xaaaa, &wdog->wsr);
+#endif /* CONFIG_WATCHDOG_RESET_DISABLE*/
 }
 
 void hw_watchdog_init(void)
@@ -33,8 +38,12 @@ void hw_watchdog_init(void)
 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
 #endif
 	timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
+#ifdef CONFIG_FSL_LSCH2
+	writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, &wdog->wcr);
+#else
 	writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
 		WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr);
+#endif /* CONFIG_FSL_LSCH2*/
 	hw_watchdog_reset();
 }
 #endif