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authorStefan Agner <stefan.agner@toradex.com>2017-09-20 13:01:11 -0700
committerMax Krummenacher <max.krummenacher@toradex.com>2017-10-02 19:36:00 +0200
commit595c17876148f4dd05d528cd5ea4ece1861b9ff9 (patch)
treee3472b21611ba980f2bf3ca80f5d0efda5e26cf2 /drivers
parentc32f05d9958ad1792318a340020b222c25795396 (diff)
mtd: nand: mxs_nand: support chips without ONFI/JEDEC parameter page
Some NAND chips do not provide a ONFI or JEDEC parameter page. In this case the driver should fallback to a sensible default. The kernel uses legacy_set_geometry to set a default geometry in this case. U-Boot does support the legacy BCH geometry too, but errors out if no ONFI/JEDEC parameter page is available. Synchronize behavior with Linux where we automatically fall back to legacy BCH geometry if no information from ONFI/JEDEC parameter page are available. Assume default chunk/step size of 512 like the Linux kernel is doing. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mtd/nand/mxs_nand.c14
1 files changed, 9 insertions, 5 deletions
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 499a6ce122e..63929ac6b62 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -201,6 +201,11 @@ static int mxs_nand_get_ecc_strength(struct mtd_info *mtd)
uint32_t page_oob_size = mtd->oobsize;
int meta = MXS_NAND_METADATA_SIZE;
int max_ecc_strength_supported;
+#if defined(CONFIG_NAND_MXS_BCH_LEGACY_GEO)
+ bool legacy_bch_geometry = true;
+#else
+ bool legacy_bch_geometry = false;
+#endif
/* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
if (is_mx6sx() || is_mx7())
@@ -215,8 +220,8 @@ static int mxs_nand_get_ecc_strength(struct mtd_info *mtd)
if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0) &&
!(page_oob_size > 1024)) {
- printf("cannot support the NAND, missing necessary info\n");
- return -EINVAL;
+ chip->ecc_step_ds = 512;
+ legacy_bch_geometry = true;
}
/* set some parameters according to NAND chip parameters */
@@ -251,15 +256,14 @@ static int mxs_nand_get_ecc_strength(struct mtd_info *mtd)
(galois_field * ecc_strength +
chunk_data_size * 8) + 1;
}
- } else {
+ } else if (!legacy_bch_geometry) {
ecc_strength = chip->ecc_strength_ds;
ecc_strength += ecc_strength & 1;
-#if defined(CONFIG_NAND_MXS_BCH_LEGACY_GEO)
+ } else {
ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
/(galois_field * mxs_nand_ecc_chunk_cnt(mtd->writesize));
ecc_strength = round_down(ecc_strength, 2);
ecc_strength = min(ecc_strength, max_ecc_strength_supported);
-#endif
}
return 0;
};