Fix Seaboard UART corruption on SPI activity

On Seaboard the UART and SPI interfere with each other. This causes the UART
to receive spurious zero bytes after SPI transactions and also means that
SPI can corrupt a few output characters when it starts up if they are still
in the UART buffer.

This hack corrects this by making SPI record that it may have corrupted the
UART, and making the UART take evasive action.

BUG=chromium-os:13228
TEST=Try developer U-Boot on Seaboard, make sure it auto-boots OK now

Review URL: http://codereview.chromium.org/6715017

Change-Id: If2281357f177eeb3a19a170ddea22adbcf5942e9
Reviewed-on: http://gerrit.chromium.org/gerrit/191
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

2 files changed, 67 insertions, 48 deletions

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index ed3428d7d8..71c523dfeb 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <config.h>
+#include <common.h>
 #include <ns16550.h>
 #include <watchdog.h>
 #include <linux/types.h>
@@ -31,6 +32,16 @@ DECLARE_GLOBAL_DATA_PTR;
 #define CONFIG_SYS_NS16550_IER  0x00
 #endif /* CONFIG_SYS_NS16550_IER */
 
+/*
+ * Signal that we are about to use the UART. This unfortunate hack is
+ * required by Seaboard, which cannot use its console and SPI at the same
+ * time. If the board file provides this, the board config will declare it.
+ * Let this be a lesson for others.
+ */
+#ifndef CONFIG_SPI_CORRUPTS_UART
+inline void uart_enable(void) {}
+#endif
+
 void NS16550_init (NS16550_t com_port, int baud_divisor)
 {
 	serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
@@ -71,10 +82,12 @@ void NS16550_reinit (NS16550_t com_port, int baud_divisor)
 	serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
 	serial_out(UART_LCRVAL, &com_port->lcr);
 }
+
 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
 
 void NS16550_putc (NS16550_t com_port, char c)
 {
+	uart_enable();
 	while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0);
 	serial_out(c, &com_port->thr);
 
@@ -92,6 +105,7 @@ void NS16550_putc (NS16550_t com_port, char c)
 
 static char NS16550_raw_getc(NS16550_t regs)
 {
+	uart_enable();
 	while ((serial_in(&regs->lsr) & UART_LSR_DR) == 0) {
 #ifdef CONFIG_USB_TTY
 		extern void usbtty_poll(void);
@@ -107,7 +121,6 @@ static int NS16550_raw_tstc(NS16550_t regs)
 	return ((serial_in(&regs->lsr) & UART_LSR_DR) != 0);
 }
 
-
 #ifdef CONFIG_NS16550_BUFFER_READS
 
 #define BUF_SIZE 256
@@ -185,8 +198,37 @@ char NS16550_getc(NS16550_t regs, unsigned int port)
 
 int NS16550_tstc(NS16550_t regs, unsigned int port)
 {
+	uart_enable();
 	return NS16550_raw_tstc(regs);
 }
 
 #endif /* CONFIG_NS16550_BUFFER_READS */
+
+/* Clear the UART's RX FIFO */
+
+void NS16550_clear(NS16550_t regs, unsigned port)
+{
+	/* Reset RX fifo */
+	serial_out(UART_FCR_FIFO_EN | UART_FCR_RXSR, &regs->fcr);
+
+	/* Remove any pending characters */
+	while (NS16550_raw_tstc(regs))
+		NS16550_raw_getc(regs);
+}
+
+/* Wait for the UART's output buffer and holding register to drain */
+
+void NS16550_drain(NS16550_t regs, unsigned port)
+{
+	u32 mask = UART_LSR_TEMT | UART_LSR_THRE;
+
+	/* Wait for the UART to finish sending */
+	while ((serial_in(&regs->lsr) & mask) != mask)
+		udelay(100);
+#ifdef CONFIG_NS16550_BUFFER_READS
+	/* Quickly grab any incoming data while we can */
+	fill_rx_buf(regs, port);
+#endif
+}
+
 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
diff --git a/drivers/spi/tegra2_spi.c b/drivers/spi/tegra2_spi.c
index 417fcc8dc7..e6ef00357e 100644
--- a/drivers/spi/tegra2_spi.c
+++ b/drivers/spi/tegra2_spi.c
@@ -24,8 +24,10 @@
 #include <common.h>
 
 #include <malloc.h>
+#include <ns16550.h> /* for NS16550_drain and NS16550_clear */
 #include <spi.h>
 #include <asm/io.h>
+#include <asm/arch/bitfield.h>
 #include <asm/arch/clk_rst.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
@@ -114,20 +116,17 @@ void spi_init(void)
 	debug("spi_init: COMMAND = %08x\n", readl(&spi->command));
 
 	/*
-	 * SPI pins on Tegra2 are muxed - change pinmux last due to UART issue
+	 * SPI pins on Tegra2 are muxed - change pinmux last due to UART
+	 * issue. GMD_SEL [31:30] = (3) SFLASH
 	 */
-	reg = readl(&pmt->pmt_ctl_c);
-	reg |= GMD_SEL_SFLASH;		/* GMD_SEL [31:30] = (3) SFLASH */
-	writel(reg, &pmt->pmt_ctl_c);
-	debug("spi_init: PinMuxRegC = %08x\n", reg);
+	bf_writel(GMD_SEL_SFLASH, 3, &pmt->pmt_ctl_c);
 
 	pinmux_tristate_disable(PIN_LSPI);
 
 	/*
 	 * NOTE:
 	 * Don't set PinMux bits 3:2 to SPI here or subsequent UART data
-	 * won't go out! It'll be correctly set in the actual SPI driver
-	 * before/after any transactions (cs_activate/_deactivate).
+	 * won't go out! It'll be correctly set in seaboard_switch_spi_uart().
 	 */
 }
 
@@ -138,64 +137,34 @@ int spi_claim_bus(struct spi_slave *slave)
 
 void spi_release_bus(struct spi_slave *slave)
 {
+	/*
+	 * We can't release UART_DISABLE and set pinmux to UART4 here since
+	 * some code (e,g, spi_flash_probe) uses printf() while the SPI
+	 * bus is held. That is arguably bad, but it has the advantage of
+	 * already being in the source tree.
+	 */
 }
 
 void spi_cs_activate(struct spi_slave *slave)
 {
-	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
 	struct spi_tegra *spi = (struct spi_tegra *)TEGRA2_SPI_BASE;
 	u32 val;
 
-	/*
-	 * Delay here to clean up comms - spurious chars seen around SPI xfers.
-	 * Fine-tune later.
-	 */
-	udelay(1000);
-
-	/* We need to dynamically change the pinmux, shared w/UART RXD/CTS */
-	val = readl(&pmt->pmt_ctl_b);
-	val |= GMC_SEL_SFLASH;		/* GMC_SEL [3:2] = (3) SFLASH */
-	writel(val, &pmt->pmt_ctl_b);
-
-	/*
-	 * On Seaboard, MOSI/MISO are shared w/UART.
-	 * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity.
-	 * Enable UART later (cs_deactivate) so we can use it for U-Boot comms.
-	 */
-	gpio_direction_output(UART_DISABLE_GPIO, 1);
+	seaboard_switch_spi_uart(SWITCH_SPI);
 
 	/* CS is negated on Tegra, so drive a 1 to get a 0 */
 	val = readl(&spi->command);
-	writel((val |= SPI_CMD_CS_VAL), &spi->command);
+	writel(val | SPI_CMD_CS_VAL, &spi->command);
 }
 
 void spi_cs_deactivate(struct spi_slave *slave)
 {
-	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
 	struct spi_tegra *spi = (struct spi_tegra *)TEGRA2_SPI_BASE;
 	u32 val;
 
-	/*
-	 * Delay here to clean up comms - spurious chars seen around SPI xfers.
-	 * Fine-tune later.
-	 */
-	udelay(1000);
-
-	/* We need to dynamically change the pinmux, shared w/UART RXD/CTS */
-	val = readl(&pmt->pmt_ctl_b);
-	val &= ~GMC_SEL_SFLASH;		/* GMC_SEL [3:2] = (0) UARTD */
-	writel(val, &pmt->pmt_ctl_b);
-
-	/*
-	 * On Seaboard, MOSI/MISO are shared w/UART.
-	 * GPIO I3 (UART_DISABLE) is used to tristate UART in cs_activate.
-	 * Enable UART here by setting that GPIO to 0 so we can do U-Boot comms.
-	 */
-	gpio_direction_output(UART_DISABLE_GPIO, 0);
-
 	/* CS is negated on Tegra, so drive a 0 to get a 1 */
 	val = readl(&spi->command);
-	writel((val &= ~SPI_CMD_CS_VAL), &spi->command);
+	writel(val & ~SPI_CMD_CS_VAL, &spi->command);
 }
 
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
@@ -235,7 +204,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 		}
 
 		num_bytes -= bytes;
-		dout     += bytes;
+		if (dout)
+			dout     += bytes;
 		bitlen   -= bits;
 
 		reg = readl(&spi->command);
@@ -281,10 +251,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 
 				/* swap bytes read in */
 				if (din != NULL) {
+					for (i = bytes - 1; i >= 0; --i) {
+						((u8 *)din)[i] =
+							(tmpdin & 0xff);
+						tmpdin >>= 8;
+					}
+/* this is not the same!
 					for (i = 0; i < bytes; ++i) {
 						((u8 *)din)[i] = (tmpdin >> 24);
 						tmpdin <<= 8;
 					}
+*/
 					din += bytes;
 				}
 			}