diff options
| author | Neil Armstrong <narmstrong@baylibre.com> | 2020-10-02 11:16:09 +0200 |
|---|---|---|
| committer | Anatolij Gustschin <agust@denx.de> | 2020-10-18 10:36:05 +0200 |
| commit | 01c9857fa806e23a30f2b042b32ceeac6bee9d36 (patch) | |
| tree | cd6cf04f0b5d465b065864ac778aa9ed3bdefb49 /drivers/video | |
| parent | b53c122631d3e88280909c04102d7859c311cdfe (diff) | |
video: dw-mipi-dsi: permit configuring the escape clock rate
The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency
higher than 10MHz for the TX Escape Clock, thus make the target rate
configurable.
This is based on the Linux commit [1] and adapted to the U-Boot driver.
[1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/dw_mipi_dsi.c | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c index 44a60ac532..4055ef49b6 100644 --- a/drivers/video/dw_mipi_dsi.c +++ b/drivers/video/dw_mipi_dsi.c @@ -485,15 +485,27 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi) { + const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops; + unsigned int esc_rate; + u32 esc_clk_division; + /* * The maximum permitted escape clock is 20MHz and it is derived from - * lanebyteclk, which is running at "lane_mbps / 8". Thus we want: + * lanebyteclk, which is running at "lane_mbps / 8". + */ + if (phy_ops->get_esc_clk_rate) + phy_ops->get_esc_clk_rate(dsi->device, &esc_rate); + else + esc_rate = 20; /* Default to 20MHz */ + + /* + * We want: * - * (lane_mbps >> 3) / esc_clk_division < 20 + * (lane_mbps >> 3) / esc_clk_division < X * which is: - * (lane_mbps >> 3) / 20 > esc_clk_division + * (lane_mbps >> 3) / X > esc_clk_division */ - u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; + esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1; dsi_write(dsi, DSI_PWR_UP, RESET); |