diff options
| author | Christian Gmeiner <christian.gmeiner@gmail.com> | 2018-05-14 11:32:17 +0200 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2018-06-13 09:50:57 +0800 |
| commit | acc2482fd8079a062c051cfaac16054f527acab4 (patch) | |
| tree | 30d47145cfaeb0ef3a6c8b8ca6d67ef8e0e6163d /drivers/timer | |
| parent | 7868909ed53ed41a945f7ed95ebb88aa252142ce (diff) | |
x86: tsc: add support for reading CPU freq from cpuid
Starting with cpuid level 0x16 (Skylake-based processors)
it is possible to get CPU base freq via cpuid.
This fixes booting on a skylake based system.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed wrong indention of labels]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'drivers/timer')
| -rw-r--r-- | drivers/timer/tsc_timer.c | 29 |
1 files changed, 24 insertions, 5 deletions
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index c7fefd2031..cf869998bf 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -21,6 +21,17 @@ DECLARE_GLOBAL_DATA_PTR; +static unsigned long cpu_mhz_from_cpuid(void) +{ + if (gd->arch.x86_vendor != X86_VENDOR_INTEL) + return 0; + + if (cpuid_eax(0) < 0x16) + return 0; + + return cpuid_eax(0x16); +} + /* * According to Intel 64 and IA-32 System Programming Guide, * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be @@ -343,13 +354,21 @@ static void tsc_timer_ensure_setup(void) if (!gd->arch.clock_rate) { unsigned long fast_calibrate; + fast_calibrate = cpu_mhz_from_cpuid(); + if (fast_calibrate) + goto done; + fast_calibrate = cpu_mhz_from_msr(); - if (!fast_calibrate) { - fast_calibrate = quick_pit_calibrate(); - if (!fast_calibrate) - panic("TSC frequency is ZERO"); - } + if (fast_calibrate) + goto done; + + fast_calibrate = quick_pit_calibrate(); + if (fast_calibrate) + goto done; + + panic("TSC frequency is ZERO"); +done: gd->arch.clock_rate = fast_calibrate * 1000000; } } |