diff options
| author | Simon Glass <sjg@chromium.org> | 2011-05-19 17:56:33 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2011-08-24 10:01:51 -0700 |
| commit | f22424f2c7b085a88eb6b750c6acca1e2d133e9c (patch) | |
| tree | 73b4d58fd2af0e64114f6b502a16cf6a33a02bd8 /drivers/spi | |
| parent | a9177e1137f15505a0a5718e46167f43baede92b (diff) | |
tegra2: Add clock and PLL control functions
This adds functions for setting up clocks to peripherals, by selecting
a parent clock and specifying a rate.
BUG=chromium-os:13228
TEST=Build, boot on Seaboard
Change-Id: I957723b5f0ef64244c16f44ae7cbd79abf06427d
Reviewed-on: http://gerrit.chromium.org/gerrit/1290
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/tegra2_spi.c | 22 |
1 files changed, 3 insertions, 19 deletions
diff --git a/drivers/spi/tegra2_spi.c b/drivers/spi/tegra2_spi.c index c6833b83d0..e200a5c7d4 100644 --- a/drivers/spi/tegra2_spi.c +++ b/drivers/spi/tegra2_spi.c @@ -26,6 +26,7 @@ #include <malloc.h> #include <ns16550.h> /* for NS16550_drain and NS16550_clear */ #include <spi.h> +#include <asm/clocks.h> #include <asm/io.h> #include <asm/arch/bitfield.h> #include <asm/arch/clk_rst.h> @@ -75,30 +76,13 @@ void spi_free_slave(struct spi_slave *slave) void spi_init(void) { - struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; struct spi_tegra *spi = (struct spi_tegra *)TEGRA2_SPI_BASE; u32 reg; - /* - * SPI reset/clocks init - reset SPI, set clocks, release from reset - */ - reset_set_enable(PERIPH_ID_SPI1, 1); - clock_enable(PERIPH_ID_SPI1); - /* Change SPI clock to 24MHz, PLLP_OUT0 source */ - reg = readl(&clkrst->crc_clk_src_spi1); - reg &= 0x3FFFFF00; /* src = PLLP_OUT0 */ - reg |= ((9-1) << 1); /* div = 9 in 7.1 format */ - writel(reg, &clkrst->crc_clk_src_spi1); - debug("spi_init: ClkSrc = %08x\n", reg); - - /* wait for 2us */ - udelay(2); - - reset_set_enable(PERIPH_ID_SPI1, 0); + clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, CLK_24M); /* Clear stale status here */ - reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \ SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF; writel(reg, &spi->status); @@ -109,7 +93,7 @@ void spi_init(void) */ reg = readl(&spi->command); - writel((reg | SPI_CMD_CS_SOFT), &spi->command); + writel(reg | SPI_CMD_CS_SOFT, &spi->command); debug("spi_init: COMMAND = %08x\n", readl(&spi->command)); /* |