diff options
| author | Pratyush Yadav <p.yadav@ti.com> | 2023-04-28 16:50:13 +0530 |
|---|---|---|
| committer | Udit Kumar <u-kumar1@ti.com> | 2023-05-22 22:07:17 +0530 |
| commit | 9a11a260b2919601cb2aa97984b9a7f99e0118ae (patch) | |
| tree | 70af33fbeb697936175dc516fe49c85d4c8b0401 /drivers/spi | |
| parent | 30647a37e52fb8249a8b2aff30752b8529452c2e (diff) | |
spi: cadence-qspi: Find the start of PHY tuning pattern in devicetree
The PHY tuning pattern should be located at the start of the partition
named "ospi.phypattern". Find it in the devicetree, if it exists.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/cadence_qspi.c | 15 | ||||
| -rw-r--r-- | drivers/spi/cadence_qspi.h | 2 |
2 files changed, 17 insertions, 0 deletions
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 456f23faca..b1dc305d15 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -206,6 +206,7 @@ static int cadence_spi_probe(struct udevice *bus) priv->trigger_address = plat->trigger_address; priv->read_delay = plat->read_delay; priv->has_phy = plat->has_phy; + priv->phy_pattern_start = plat->phy_pattern_start; priv->ahbsize = plat->ahbsize; priv->max_hz = plat->max_hz; @@ -389,6 +390,8 @@ static int cadence_spi_of_to_plat(struct udevice *bus) struct cadence_spi_plat *plat = dev_get_plat(bus); struct cadence_spi_priv *priv = dev_get_priv(bus); ofnode subnode; + const char *label; + u32 start; plat->regbase = (void *)devfdt_get_addr_index(bus, 0); plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1, @@ -435,6 +438,18 @@ static int cadence_spi_of_to_plat(struct udevice *bus) -1); plat->has_phy = ofnode_read_bool(subnode, "cdns,phy-mode"); + /* Find the PHY tuning pattern partition. */ + subnode = ofnode_first_subnode(subnode); + while (ofnode_valid(subnode)) { + label = ofnode_read_string(subnode, "label"); + if (label && strcmp(label, "ospi.phypattern") == 0) { + if (!ofnode_read_u32_array(subnode, "reg", &start, 1)) + plat->phy_pattern_start = start; + break; + } + subnode = ofnode_next_subnode(subnode); + } + debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz, plat->page_size); diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 01611ae10d..ef8ac00994 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -209,6 +209,7 @@ struct cadence_spi_plat { bool use_dac_mode; int read_delay; bool has_phy; + u32 phy_pattern_start; /* Flash parameters */ u32 page_size; @@ -241,6 +242,7 @@ struct cadence_spi_priv { u32 wr_delay; int read_delay; bool has_phy; + u32 phy_pattern_start; struct reset_ctl_bulk *resets; u32 page_size; |