diff options
| author | Vignesh R <vigneshr@ti.com> | 2016-07-06 10:20:55 +0530 |
|---|---|---|
| committer | Jagan Teki <jteki@openedev.com> | 2016-07-09 20:16:32 +0530 |
| commit | dac3bf20fb2c9b03476be0d73db620f62ab3cee1 (patch) | |
| tree | baae7a2ca8cd9342f5879bcfca6e20495037a455 /drivers/spi | |
| parent | fdf02a36c52cb96717b64113775c4251ecd49596 (diff) | |
spi: cadence_qspi_apb: Support 32 bit AHB address
AHB address can be as long as 32 bit, hence remove the
CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT
and read as u32 value, it anyway does not make sense to mask upper bits.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index a71531d309..a8cc23f0b6 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -45,7 +45,6 @@ #define CQSPI_INST_TYPE_QUAD (2) #define CQSPI_STIG_DATA_LEN_MAX (8) -#define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF) #define CQSPI_DUMMY_CLKS_PER_BYTE (8) #define CQSPI_DUMMY_BYTES_MAX (4) @@ -573,7 +572,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, addr_bytes = cmdlen - 1; /* Setup the indirect trigger address */ - writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */ @@ -714,7 +713,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, return -EINVAL; } /* Setup the indirect trigger address */ - writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */ |