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authorBin Meng <bmeng.cn@gmail.com>2017-08-15 22:38:29 -0700
committerBin Meng <bmeng.cn@gmail.com>2017-08-24 11:00:47 +0800
commit3e7914168413f7aa05a68a53ca16e84b14d6851b (patch)
tree2075a06bd7412b38f5a2b08aacc15a5a59f20606 /drivers/spi/ich.h
parent7d8297892715563a7d9ff6ff90876fd7cbeddd30 (diff)
x86: ich-spi: Don't read cached lock status
At present the ICH SPI controller driver reads the controller lock status from its register in the probe routine and saves the lock status to a member of priv. Later the driver uses the cached status from priv to judge whether the controller setting is locked and do different setup. But such logic is only valid when there is only the SPI controller driver that touches the SPI hardware. In fact the lock status change can be trigged outside the driver, eg: during the fsp_notify() call when Intel FSP is used. This changes the driver to read the lock status every time when an SPI transfer is initiated instead of reading the cached one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/spi/ich.h')
-rw-r--r--drivers/spi/ich.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
index dcb8a9048f8..c867c57be9f 100644
--- a/drivers/spi/ich.h
+++ b/drivers/spi/ich.h
@@ -177,8 +177,6 @@ struct ich_spi_platdata {
};
struct ich_spi_priv {
- int ichspi_lock;
- int locked;
int opmenu;
int menubytes;
void *base; /* Base of register set */