diff options
author | Tom Rini <trini@konsulko.com> | 2021-08-27 08:33:02 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2021-08-27 08:33:02 -0400 |
commit | b9cb74a5aa256fc34a1b2b9dd847a985b91f34f6 (patch) | |
tree | a618344b253ec3164848e797a2636bbd8f060223 /drivers/soc/soc_xilinx_versal.c | |
parent | 7bfa565453ec5f63668a3464da21629055c3053f (diff) | |
parent | 229cb5c6ba3469cbc4a0bcc69389fe61c51fd3b4 (diff) |
Merge tag 'xilinx-for-v2021.10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.10-rc3
xilinx:
- Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
- Print information about cpu via soc drivers and enable DISPLAY_CPUINFO
- Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT
zynq:
- Wire single QSPI
- Use power-source instead of io-standard properties
- Enable nor on zc770-xm012
zynqmp:
- Change handling around multi_boot()
- Setup offset for u-boot.itb in spi
- Generate run time dfu_alt_info for capsule update
- Use explicit values for enums (zynqmp_firmware.h)
- Enable RTC/SHA1/BUTTON/BUTTON_GPIO command
- Disable WDT driver by default
- Bind usb/scsi via preboot because of EFI
- DT updates/fixes
- Add soc driver
- Fix SPL SPI boot mode
versal:
- Add soc driver
sdhci:
- Update tap delay programming for zynq_sdhci driver
cmd:
- Fix RTC uclass handling in date command
- Update pwm help message
- Update reset help message
watchdog:
- Fix wwdt compilation
rtc:
- Deal with seq alias in rtc uclass
- Add zynqmp RTC driver
fdt:
- Add kernel-doc for fdt_fixup_memory_banks()
Diffstat (limited to 'drivers/soc/soc_xilinx_versal.c')
-rw-r--r-- | drivers/soc/soc_xilinx_versal.c | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/drivers/soc/soc_xilinx_versal.c b/drivers/soc/soc_xilinx_versal.c new file mode 100644 index 0000000000..f8bcd9ab40 --- /dev/null +++ b/drivers/soc/soc_xilinx_versal.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal SOC driver + * + * Copyright (C) 2021 Xilinx, Inc. + */ + +#include <common.h> +#include <dm.h> +#include <soc.h> +#include <zynqmp_firmware.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +/* + * v1 -> 0x10 - ES1 + * v2 -> 0x20 - Production + */ +static const char versal_family[] = "Versal"; + +struct soc_xilinx_versal_priv { + const char *family; + char revision; +}; + +static int soc_xilinx_versal_get_family(struct udevice *dev, char *buf, int size) +{ + struct soc_xilinx_versal_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "%s", priv->family); +} + +static int soc_xilinx_versal_get_revision(struct udevice *dev, char *buf, int size) +{ + struct soc_xilinx_versal_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "v%d", priv->revision); +} + +static const struct soc_ops soc_xilinx_versal_ops = { + .get_family = soc_xilinx_versal_get_family, + .get_revision = soc_xilinx_versal_get_revision, +}; + +static int soc_xilinx_versal_probe(struct udevice *dev) +{ + struct soc_xilinx_versal_priv *priv = dev_get_priv(dev); + u32 ret_payload[4]; + int ret; + + priv->family = versal_family; + + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) { + ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, + ret_payload); + if (ret) + return ret; + } else { + ret_payload[2] = readl(VERSAL_PS_PMC_VERSION); + if (!ret_payload[2]) + return -EINVAL; + } + + priv->revision = ret_payload[2] >> VERSAL_PS_VER_SHIFT; + + return 0; +} + +U_BOOT_DRIVER(soc_xilinx_versal) = { + .name = "soc_xilinx_versal", + .id = UCLASS_SOC, + .ops = &soc_xilinx_versal_ops, + .probe = soc_xilinx_versal_probe, + .priv_auto = sizeof(struct soc_xilinx_versal_priv), + .flags = DM_FLAG_PRE_RELOC, +}; |