diff options
| author | Robert Marko <robert.marko@sartura.hr> | 2020-07-06 10:37:55 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-07-29 08:43:40 -0400 |
| commit | 185dcf7f56dde4953ccb8b43355355e86376efb8 (patch) | |
| tree | 5f241f0ede1f1bde4dfbf667004f125d59f3a556 /drivers/serial | |
| parent | e479a7d52e5d6804c0a7adaac7a20c9713d2544a (diff) | |
msm_serial: Read bit rate register value from DT
IPQ40xx and currently supported Snapdragon boards don't use the same one
so enable reading it from DT, if no DT property is found default value
is the same as the previous define.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Diffstat (limited to 'drivers/serial')
| -rw-r--r-- | drivers/serial/serial_msm.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index a1c9abcfbb..c8946c3aae 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -61,6 +61,7 @@ struct msm_serial_data { phys_addr_t base; unsigned chars_cnt; /* number of buffered chars */ uint32_t chars_buf; /* buffered chars */ + uint32_t clk_bit_rate; /* data mover mode bit rate register value */ }; static int msm_serial_fetch(struct udevice *dev) @@ -190,7 +191,7 @@ static int msm_uart_clk_init(struct udevice *dev) static void uart_dm_init(struct msm_serial_data *priv) { - writel(UART_DM_CLK_RX_TX_BIT_RATE, priv->base + UARTDM_CSR); + writel(priv->clk_bit_rate, priv->base + UARTDM_CSR); writel(0x0, priv->base + UARTDM_MR1); writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2); writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR); @@ -223,6 +224,9 @@ static int msm_serial_ofdata_to_platdata(struct udevice *dev) if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; + priv->clk_bit_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "bit-rate", UART_DM_CLK_RX_TX_BIT_RATE); + return 0; } |