diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2018-04-12 17:39:46 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2018-05-11 09:38:23 +0200 |
| commit | 1d6c54ecb39b8591a98f02f9b47af225ff07cd0b (patch) | |
| tree | 4984d843cbc1da3774ac6b82cd556ac8313da7b8 /drivers/serial | |
| parent | 6915dcf35987d654b491524f151e56b91e0d0ec9 (diff) | |
arm: zynqmp: Add ZynqMP minimal R5 support
Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
This patch is adding minimal support to get U-Boot boot.
U-Boot on R5 runs out of DDR with default configuration that's why
DDR needs to be partitioned if there is something else running on arm64.
Console is done via Cadence uart driver and the first Cadence Triple
Timer Counter is used for time.
This configuration with uart1 was tested on zcu100-revC.
U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200)
Model: Xilinx ZynqMP R5
DRAM: 512 MiB
WARNING: Caches not enabled
MMC:
In: serial@ff010000
Out: serial@ff010000
Err: serial@ff010000
Net: Net Initialization Skipped
No ethernet found.
ZynqMP r5>
There are two ways how to run this on ZynqMP.
1. Run from ZynqMP arm64
tftpb 20000000 u-boot-r5.elf
setenv autostart no && bootelf -p 20000000
cpu 4 disable && cpu 4 release 10000000 lockstep
or
cpu 4 disable && cpu 4 release 10000000 split
2. Load via jtag when directly to R5
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/serial')
| -rw-r--r-- | drivers/serial/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 4be8868536..5937910e5b 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -624,7 +624,7 @@ config STM32_SERIAL config ZYNQ_SERIAL bool "Cadence (Xilinx Zynq) UART support" - depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) + depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_ZYNQMP_R5) help This driver supports the Cadence UART. It is found e.g. in Xilinx Zynq/ZynqMP. |