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authorStephen Warren <swarren@nvidia.com>2016-08-08 11:28:25 -0600
committerTom Warren <twarren@nvidia.com>2016-08-15 10:26:13 -0700
commit4dd99d140cf061478d1ac9e0a961a3874b759f1d (patch)
tree483727d1b1d0aa3b9ade98ce696a1226601384d6 /drivers/reset
parentd9fd7008f48ba3361133e3b901322a724fd2aced (diff)
reset: add Tegra186 reset driver
In Tegra186, on-SoC reset signals are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'drivers/reset')
-rw-r--r--drivers/reset/Kconfig7
-rw-r--r--drivers/reset/Makefile1
-rw-r--r--drivers/reset/tegra186-reset.c81
3 files changed, 89 insertions, 0 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 0fe8cc3827..5b84f2178b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -20,4 +20,11 @@ config SANDBOX_RESET
simply accepts requests to reset various HW modules without actually
doing anything beyond a little error checking.
+config TEGRA186_RESET
+ bool "Enable Tegra186 BPMP-based reset driver"
+ depends on TEGRA186_BPMP
+ help
+ Enable support for manipulating Tegra's on-SoC reset signals via IPC
+ requests to the BPMP (Boot and Power Management Processor).
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 71f3b21961..ff0e090775 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_DM_RESET) += reset-uclass.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
+obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
diff --git a/drivers/reset/tegra186-reset.c b/drivers/reset/tegra186-reset.c
new file mode 100644
index 0000000000..228adda0aa
--- /dev/null
+++ b/drivers/reset/tegra186-reset.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <misc.h>
+#include <reset-uclass.h>
+#include <asm/arch-tegra/bpmp_abi.h>
+
+static int tegra186_reset_request(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return 0;
+}
+
+static int tegra186_reset_free(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return 0;
+}
+
+static int tegra186_reset_common(struct reset_ctl *reset_ctl,
+ enum mrq_reset_commands cmd)
+{
+ struct mrq_reset_request req;
+ int ret;
+
+ req.cmd = cmd;
+ req.reset_id = reset_ctl->id;
+
+ ret = misc_call(reset_ctl->dev->parent, MRQ_RESET, &req, sizeof(req),
+ NULL, 0);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int tegra186_reset_assert(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return tegra186_reset_common(reset_ctl, CMD_RESET_ASSERT);
+}
+
+static int tegra186_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return tegra186_reset_common(reset_ctl, CMD_RESET_DEASSERT);
+}
+
+struct reset_ops tegra186_reset_ops = {
+ .request = tegra186_reset_request,
+ .free = tegra186_reset_free,
+ .rst_assert = tegra186_reset_assert,
+ .rst_deassert = tegra186_reset_deassert,
+};
+
+static int tegra186_reset_probe(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(tegra186_reset) = {
+ .name = "tegra186_reset",
+ .id = UCLASS_RESET,
+ .probe = tegra186_reset_probe,
+ .ops = &tegra186_reset_ops,
+};