diff options
| author | Jagan Teki <jagan@amarulasolutions.com> | 2019-07-16 17:27:14 +0530 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-07-20 23:59:44 +0800 |
| commit | 009fe1bac96889bd5f10f8d7a3edf4f1ba125ff3 (patch) | |
| tree | 3620cae4c81c8e6d350909d598ae1b69bb43f716 /drivers/ram | |
| parent | 47627c8a5cfc0d5d60ca81446528705b3b56077b (diff) | |
ram: rk3399: Configure PHY_898, PHY_919 for lpddr4
PHY_898, PHY_919 would require to configure PHY LP4 boot
pll control and ca for lpddr4.
So, configure the same in pctl_cfg for LPDDR4.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/ram')
| -rw-r--r-- | drivers/ram/rockchip/sdram_rk3399.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 8b2c6b3cdb..aaf786a03e 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -574,6 +574,11 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, writel(params->phy_regs.denali_phy[911], &denali_phy[911]); writel(params->phy_regs.denali_phy[912], &denali_phy[912]); + if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) { + writel(params->phy_regs.denali_phy[898], &denali_phy[898]); + writel(params->phy_regs.denali_phy[919], &denali_phy[919]); + } + dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); |