diff options
| author | Patrick Delaunay <patrick.delaunay@st.com> | 2019-04-10 14:09:22 +0200 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@st.com> | 2019-05-23 11:38:10 +0200 |
| commit | 0cb1aa94093c22dd5b3dce32d371e154abc06ffe (patch) | |
| tree | 49ed36ed0ab1c83ab82b0aa849454638365460f0 /drivers/ram | |
| parent | c3ec370aed1d64c70578b22b18bed5c05f040962 (diff) | |
stm32mp1: ram: increase the delay after reset to 128 cycles
Component Notification DDR controller errata (3.00a):9001313030
Synchronization Time Waited After De-assertion of presetn is
128 pclk Cycles.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'drivers/ram')
| -rw-r--r-- | drivers/ram/stm32mp1/stm32mp1_ddr.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c index caa7813d44..82003667de 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -401,11 +401,9 @@ void stm32mp1_ddr_init(struct ddr_info *priv, */ clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); -/* 1.4. wait 4 cycles for synchronization */ - asm(" nop"); - asm(" nop"); - asm(" nop"); - asm(" nop"); +/* 1.4. wait 128 cycles to permit initialization of end logic */ + udelay(2); + /* for PCLK = 133MHz => 1 us is enough, 2 to allow lower frequency */ /* 1.5. initialize registers ddr_umctl2 */ /* Stop uMCTL2 before PHY is ready */ |