diff options
| author | Haiying Wang <Haiying.Wang@freescale.com> | 2009-05-21 15:32:13 -0400 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-06-12 17:16:25 -0500 |
| commit | 52d6ad5ecfb22938441c8e3e62935fbd7b0f0920 (patch) | |
| tree | 5d6f55283f11e7cea73bcf34b76a126c0d3821bd /drivers/qe | |
| parent | feb7838f979ec2b581df3c791b9ae3284c36bb47 (diff) | |
drivers/qe: Rename the camel-case identifiers in uec
Rename riscRx/riscTx to risc_rx/risc_tx to comply with Codingstyle.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Diffstat (limited to 'drivers/qe')
| -rw-r--r-- | drivers/qe/uec.c | 32 | ||||
| -rw-r--r-- | drivers/qe/uec.h | 4 |
2 files changed, 18 insertions, 18 deletions
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index bba3ef2c66a..e67c0bab644 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -46,8 +46,8 @@ static uec_info_t eth1_uec_info = { .num_threads_tx = UEC_NUM_OF_THREADS_4, .num_threads_rx = UEC_NUM_OF_THREADS_4, #endif - .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, - .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, .phy_address = CONFIG_SYS_UEC1_PHY_ADDR, @@ -69,8 +69,8 @@ static uec_info_t eth2_uec_info = { .num_threads_tx = UEC_NUM_OF_THREADS_4, .num_threads_rx = UEC_NUM_OF_THREADS_4, #endif - .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, - .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, .phy_address = CONFIG_SYS_UEC2_PHY_ADDR, @@ -92,8 +92,8 @@ static uec_info_t eth3_uec_info = { .num_threads_tx = UEC_NUM_OF_THREADS_4, .num_threads_rx = UEC_NUM_OF_THREADS_4, #endif - .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, - .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, .phy_address = CONFIG_SYS_UEC3_PHY_ADDR, @@ -115,8 +115,8 @@ static uec_info_t eth4_uec_info = { .num_threads_tx = UEC_NUM_OF_THREADS_4, .num_threads_rx = UEC_NUM_OF_THREADS_4, #endif - .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, - .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, .phy_address = CONFIG_SYS_UEC4_PHY_ADDR, @@ -138,8 +138,8 @@ static uec_info_t eth5_uec_info = { .num_threads_tx = UEC_NUM_OF_THREADS_4, .num_threads_rx = UEC_NUM_OF_THREADS_4, #endif - .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, - .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, .phy_address = CONFIG_SYS_UEC5_PHY_ADDR, @@ -161,8 +161,8 @@ static uec_info_t eth6_uec_info = { .num_threads_tx = UEC_NUM_OF_THREADS_4, .num_threads_rx = UEC_NUM_OF_THREADS_4, #endif - .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, - .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, .phy_address = CONFIG_SYS_UEC6_PHY_ADDR, @@ -1020,7 +1020,7 @@ static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec, /* Init Rx global parameter pointer */ p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset | - (u32)uec_info->riscRx; + (u32)uec_info->risc_rx; /* Init Rx threads */ for (i = 0; i < (thread_rx + 1); i++) { @@ -1038,13 +1038,13 @@ static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec, } entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) | - init_enet_offset | (u32)uec_info->riscRx; + init_enet_offset | (u32)uec_info->risc_rx; p_init_enet_param->rxthread[i] = entry_val; } /* Init Tx global parameter pointer */ p_init_enet_param->txglobal = uec->tx_glbl_pram_offset | - (u32)uec_info->riscTx; + (u32)uec_info->risc_tx; /* Init Tx threads */ for (i = 0; i < thread_tx; i++) { @@ -1057,7 +1057,7 @@ static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec, UEC_THREAD_TX_PRAM_ALIGNMENT); entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) | - init_enet_offset | (u32)uec_info->riscTx; + init_enet_offset | (u32)uec_info->risc_tx; p_init_enet_param->txthread[i] = entry_val; } diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 0b644996b55..414982cdec9 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -654,8 +654,8 @@ typedef struct uec_info { ucc_fast_info_t uf_info; uec_num_of_threads_e num_threads_tx; uec_num_of_threads_e num_threads_rx; - qe_risc_allocation_e riscTx; - qe_risc_allocation_e riscRx; + qe_risc_allocation_e risc_tx; + qe_risc_allocation_e risc_rx; u16 rx_bd_ring_len; u16 tx_bd_ring_len; u8 phy_address; |