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authorTom Rini <trini@konsulko.com>2022-02-21 08:32:02 -0500
committerTom Rini <trini@konsulko.com>2022-02-21 08:32:02 -0500
commit24b628a8f844868adca897aae40af6f98cdbc26d (patch)
tree43572009123231107d618dce3a4f84d7e2c536d6 /drivers/power/domain/zynqmp-power-domain.c
parent55e9cef1432ffd42559874b2a469729f20b627d9 (diff)
parent9bd4232f958b94fdd700e44897fb61bdc898b787 (diff)
Merge tag 'xilinx-for-v2022.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.04-rc3 microblaze: - Fix exception handler zynqmp: - Show information about secure images - DT changes (som u-boot file removal) - Fix zynqmp_pm_cfg_obj_convert.py - Fix platform boot xilinx: - Fix bootm_size calculation - Remove GPIO_EXTRA_HEADER selection power: - Add zynqmp power management driver scsi: - Add phy support to ceva driver zynq qspi: - Fix unaligned accesses and check baudrate setup - Add support for spi memory operations net: - Fix 64bit calculation in axi_emac video: - Add missing gpio dependency for seps driver
Diffstat (limited to 'drivers/power/domain/zynqmp-power-domain.c')
-rw-r--r--drivers/power/domain/zynqmp-power-domain.c89
1 files changed, 89 insertions, 0 deletions
diff --git a/drivers/power/domain/zynqmp-power-domain.c b/drivers/power/domain/zynqmp-power-domain.c
new file mode 100644
index 0000000000..5383d09896
--- /dev/null
+++ b/drivers/power/domain/zynqmp-power-domain.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021, Xilinx. Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <misc.h>
+#include <power-domain-uclass.h>
+#include <linux/bitops.h>
+
+#include <zynqmp_firmware.h>
+
+#define NODE_ID_LOCATION 5
+
+static unsigned int xpm_configobject[] = {
+ /* HEADER */
+ 2, /* Number of remaining words in the header */
+ 1, /* Number of sections included in config object */
+ PM_CONFIG_OBJECT_TYPE_OVERLAY, /* Type of Config object as overlay */
+ /* SLAVE SECTION */
+
+ PM_CONFIG_SLAVE_SECTION_ID, /* Section ID */
+ 1, /* Number of slaves */
+
+ 0, /* Node ID which will be changed below */
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK |
+ PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK |
+ PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+};
+
+static int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
+ const u32 qos, const enum zynqmp_pm_request_ack ack)
+{
+ return xilinx_pm_request(PM_REQUEST_NODE, node, capabilities,
+ qos, ack, NULL);
+}
+
+static int zynqmp_power_domain_request(struct power_domain *power_domain)
+{
+ /* Record power domain id */
+ xpm_configobject[NODE_ID_LOCATION] = power_domain->id;
+
+ zynqmp_pmufw_load_config_object(xpm_configobject, sizeof(xpm_configobject));
+
+ return 0;
+}
+
+static int zynqmp_power_domain_free(struct power_domain *power_domain)
+{
+ /* nop now */
+ return 0;
+}
+
+static int zynqmp_power_domain_on(struct power_domain *power_domain)
+{
+ return zynqmp_pm_request_node(power_domain->id,
+ ZYNQMP_PM_CAPABILITY_ACCESS,
+ ZYNQMP_PM_MAX_QOS,
+ ZYNQMP_PM_REQUEST_ACK_BLOCKING);
+}
+
+static int zynqmp_power_domain_off(struct power_domain *power_domain)
+{
+ /* nop now */
+ return 0;
+}
+
+struct power_domain_ops zynqmp_power_domain_ops = {
+ .request = zynqmp_power_domain_request,
+ .rfree = zynqmp_power_domain_free,
+ .on = zynqmp_power_domain_on,
+ .off = zynqmp_power_domain_off,
+};
+
+static int zynqmp_power_domain_probe(struct udevice *dev)
+{
+ return 0;
+}
+
+U_BOOT_DRIVER(zynqmp_power_domain) = {
+ .name = "zynqmp_power_domain",
+ .id = UCLASS_POWER_DOMAIN,
+ .probe = zynqmp_power_domain_probe,
+ .ops = &zynqmp_power_domain_ops,
+};