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authorPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>2017-03-24 19:24:23 +0100
committerSimon Glass <sjg@chromium.org>2017-04-04 20:01:57 -0600
commit476f7090bf49ecbed8ae5350547ae8ab5165d9e1 (patch)
treefefe63449792c18c119f31c8e922fae41b7debd0 /drivers/pinctrl
parentf93a51186a894c19e998dcffd7713449de6dbad3 (diff)
rockchip: pinctrl: rk3399: add GMAC (RGMII only) support
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this point), we need support for additional pin-configuration. This commit adds the pinctrl support for GMAC in RGMII signalling mode: * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID * adds the required defines (in the GRF support) for configuring the GPIOC pins for RGMII * configures the RGMII pins (in GPIOC) when requested via pinctrl X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/rockchip/pinctrl_rk3399.c42
1 files changed, 42 insertions, 0 deletions
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index a74793aa485..507bec4a969 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -202,6 +202,39 @@ static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
}
}
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id)
+{
+ rk_clrsetreg(&grf->gpio3a_iomux,
+ GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK |
+ GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK |
+ GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK |
+ GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK,
+ GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT |
+ GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT |
+ GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT |
+ GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT |
+ GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT |
+ GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT |
+ GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT |
+ GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio3b_iomux,
+ GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK |
+ GRF_GPIO3B3_SEL_MASK |
+ GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK |
+ GRF_GPIO3B6_SEL_MASK,
+ GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT |
+ GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT |
+ GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT |
+ GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT |
+ GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT |
+ GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio3c_iomux,
+ GRF_GPIO3C1_SEL_MASK,
+ GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT);
+}
+#endif
+
static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
{
struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
@@ -243,6 +276,11 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
case PERIPH_ID_SDMMC1:
pinctrl_rk3399_sdmmc_config(priv->grf, func);
break;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case PERIPH_ID_GMAC:
+ pinctrl_rk3399_gmac_config(priv->grf, func);
+ break;
+#endif
default:
return -EINVAL;
}
@@ -283,6 +321,10 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
return PERIPH_ID_I2C5;
case 65:
return PERIPH_ID_SDMMC1;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case 12:
+ return PERIPH_ID_GMAC;
+#endif
}
#endif
return -ENOENT;