diff options
| author | Tom Rini <trini@konsulko.com> | 2019-06-20 09:14:35 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-06-20 09:14:35 -0400 |
| commit | f643fb9f4c8fc5c5dceb8c2c2893447d18413d77 (patch) | |
| tree | 9b77dd853b6027698069c5882a237778ad69e576 /drivers/pci/pcie_fsl.h | |
| parent | e8c185bb15f7e362f0d77e042b6811966917a6b7 (diff) | |
| parent | 70833d530e3b9a776c5127487c7d3c1a1bb238cc (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
- PCIe driver change to support DM model
- T2080QDS migrated to use PCIe DM model
Diffstat (limited to 'drivers/pci/pcie_fsl.h')
| -rw-r--r-- | drivers/pci/pcie_fsl.h | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h new file mode 100644 index 00000000000..5eefc31fa9a --- /dev/null +++ b/drivers/pci/pcie_fsl.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + * + * PCIe DM U-Boot driver for Freescale PowerPC SoCs + * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> + */ + +#ifndef _PCIE_FSL_H_ +#define _PCIE_FSL_H_ + +#ifdef CONFIG_SYS_FSL_PCI_VER_3_X +#define FSL_PCIE_CAP_ID 0x70 +#else +#define FSL_PCIE_CAP_ID 0x4c +#endif +/* PCIe Device Control Register */ +#define PCI_DCR (FSL_PCIE_CAP_ID + 0x08) +/* PCIe Device Status Register */ +#define PCI_DSR (FSL_PCIE_CAP_ID + 0x0a) +/* PCIe Link Control Register */ +#define PCI_LCR (FSL_PCIE_CAP_ID + 0x10) +/* PCIe Link Status Register */ +#define PCI_LSR (FSL_PCIE_CAP_ID + 0x12) + +#ifndef CONFIG_SYS_PCI_MEMORY_BUS +#define CONFIG_SYS_PCI_MEMORY_BUS 0 +#endif + +#ifndef CONFIG_SYS_PCI_MEMORY_PHYS +#define CONFIG_SYS_PCI_MEMORY_PHYS 0 +#endif + +#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) +#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024) +#endif + +#define PEX_CSR0_LTSSM_MASK 0xFC +#define PEX_CSR0_LTSSM_SHIFT 2 +#define LTSSM_L0_REV3 0x11 +#define LTSSM_L0 0x16 + +struct fsl_pcie { + int idx; + struct udevice *bus; + void __iomem *regs; + u32 law_trgt_if; /* LAW target ID */ + u32 block_rev; /* IP block revision */ + bool mode; /* RC&EP mode flag */ + bool enabled; /* Enable status */ + struct list_head list; +}; + +extern struct list_head fsl_pcie_list; + +#endif /* _PCIE_FSL_H_ */ |