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authorSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>2016-05-16 15:31:38 +0530
committerMichal Simek <michal.simek@xilinx.com>2016-11-15 15:28:01 +0100
commit4eaf8f5424ccfc2c285a70b9a337e5b39d9e39e7 (patch)
tree93ee8534b6da7ea7a4cc5960b83f937cba188d61 /drivers/net/zynq_gem.c
parent27183d7c22c35f648474e646171997eaef83947b (diff)
net: zynq_gem: Correct SGMII enable bit setting
Correct the SGMII enable bit position to 27 instead of 31. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'drivers/net/zynq_gem.c')
-rw-r--r--drivers/net/zynq_gem.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 0023b1689e..3319e10467 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -57,7 +57,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
-#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x80000000 /* SGMII Enable */
+#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
#ifdef CONFIG_ARM64
#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */