diff options
| author | Alex Marginean <alexandru.marginean@nxp.com> | 2019-07-03 12:11:41 +0300 |
|---|---|---|
| committer | Joe Hershberger <joe.hershberger@ni.com> | 2019-07-25 13:13:30 -0500 |
| commit | 1d99534beffea9b8e54a2cf31776cff68c4fc676 (patch) | |
| tree | cb93b2ec2fb678e44c791a466b643300a015a5f9 /drivers/net/fsl_enetc.h | |
| parent | 120b5ef2876c3a3aa2addaba0179791ddcbe8b58 (diff) | |
drivers: net: add NXP ENETC MDIO driver
Adds a driver for the MDIO interface currently integrated in LS1028A SoC.
This MDIO interface is shared by multiple ethernet interfaces and is
presented as a stand-alone PCI function on the SoC ECAM.
Ethernet has a functional dependency on MDIO, for simplicity there is a
single config option for both.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'drivers/net/fsl_enetc.h')
| -rw-r--r-- | drivers/net/fsl_enetc.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h index 155ecc895bc..fbb9dfa15e4 100644 --- a/drivers/net/fsl_enetc.h +++ b/drivers/net/fsl_enetc.h @@ -11,6 +11,7 @@ /* PCI function IDs */ #define PCI_DEVICE_ID_ENETC_ETH 0xE100 +#define PCI_DEVICE_ID_ENETC_MDIO 0xEE01 /* ENETC Ethernet controller registers */ /* Station interface register offsets */ @@ -143,6 +144,8 @@ struct enetc_priv { /* Rx/Tx buffer descriptor rings info */ struct bd_ring tx_bdr; struct bd_ring rx_bdr; + + int if_type; }; /* register accessors */ @@ -165,4 +168,22 @@ struct enetc_priv { #define enetc_bdr_write(priv, t, n, off, val) \ enetc_write(priv, ENETC_BDR(t, n, off), val) +/* ENETC external MDIO registers */ +#define ENETC_MDIO_BASE 0x1c00 +#define ENETC_MDIO_CFG 0x00 +#define ENETC_EMDIO_CFG_C22 0x00809508 +#define ENETC_EMDIO_CFG_C45 0x00809548 +#define ENETC_EMDIO_CFG_RD_ER BIT(1) +#define ENETC_EMDIO_CFG_BSY BIT(0) +#define ENETC_MDIO_CTL 0x04 +#define ENETC_MDIO_CTL_READ BIT(15) +#define ENETC_MDIO_DATA 0x08 +#define ENETC_MDIO_STAT 0x0c + +#define ENETC_MDIO_READ_ERR 0xffff + +struct enetc_mdio_priv { + void *regs_base; +}; + #endif /* _ENETC_H */ |