net: altera_tse: add mSG-DMA support

The Modular Scatter-Gather DMA core is a new DMA core to work
with the Altera Triple-Speed Ethernet MegaCore. It replaces the
legacy Scatter-Gather Direct Memory Access (SG-DMA) controller
core. Please find details on the "Embedded Peripherals IP User
Guide" of Altera.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Marek Vasut <marex@denx.de>

1 files changed, 60 insertions, 0 deletions

diff --git a/drivers/net/altera_tse.h b/drivers/net/altera_tse.h
index fae2378dbb..2b1af81429 100644
--- a/drivers/net/altera_tse.h
+++ b/drivers/net/altera_tse.h
@@ -15,6 +15,7 @@
 
 /* dma type */
 #define ALT_SGDMA	0
+#define ALT_MSGDMA	1
 
 /* SGDMA Stuff */
 #define ALT_SGDMA_STATUS_BUSY_MSK				BIT(4)
@@ -87,6 +88,64 @@ struct alt_sgdma_registers {
 	u32 descriptor_pad[3];
 };
 
+/* mSGDMA Stuff */
+
+/* mSGDMA extended descriptor format */
+struct msgdma_extended_desc {
+	u32 read_addr_lo;	/* data buffer source address low bits */
+	u32 write_addr_lo;	/* data buffer destination address low bits */
+	u32 len;
+	u32 burst_seq_num;
+	u32 stride;
+	u32 read_addr_hi;	/* data buffer source address high bits */
+	u32 write_addr_hi;	/* data buffer destination address high bits */
+	u32 control;		/* characteristics of the transfer */
+};
+
+/* mSGDMA descriptor control field bit definitions */
+#define MSGDMA_DESC_CTL_GEN_SOP		BIT(8)
+#define MSGDMA_DESC_CTL_GEN_EOP		BIT(9)
+#define MSGDMA_DESC_CTL_END_ON_EOP	BIT(12)
+#define MSGDMA_DESC_CTL_END_ON_LEN	BIT(13)
+#define MSGDMA_DESC_CTL_GO		BIT(31)
+
+/* Tx buffer control flags */
+#define MSGDMA_DESC_CTL_TX_SINGLE	(MSGDMA_DESC_CTL_GEN_SOP |	\
+					 MSGDMA_DESC_CTL_GEN_EOP |	\
+					 MSGDMA_DESC_CTL_GO)
+
+#define MSGDMA_DESC_CTL_RX_SINGLE	(MSGDMA_DESC_CTL_END_ON_EOP |	\
+					 MSGDMA_DESC_CTL_END_ON_LEN |	\
+					 MSGDMA_DESC_CTL_GO)
+
+/* mSGDMA extended descriptor stride definitions */
+#define MSGDMA_DESC_TX_STRIDE		0x00010001
+#define MSGDMA_DESC_RX_STRIDE		0x00010001
+
+/* mSGDMA dispatcher control and status register map */
+struct msgdma_csr {
+	u32 status;		/* Read/Clear */
+	u32 control;		/* Read/Write */
+	u32 rw_fill_level;
+	u32 resp_fill_level;	/* bit 15:0 */
+	u32 rw_seq_num;
+	u32 pad[3];		/* reserved */
+};
+
+/* mSGDMA CSR status register bit definitions */
+#define MSGDMA_CSR_STAT_BUSY			BIT(0)
+#define MSGDMA_CSR_STAT_RESETTING		BIT(6)
+#define MSGDMA_CSR_STAT_MASK			0x3FF
+
+/* mSGDMA CSR control register bit definitions */
+#define MSGDMA_CSR_CTL_RESET			BIT(1)
+
+/* mSGDMA response register map */
+struct msgdma_response {
+	u32 bytes_transferred;
+	u32 status;
+};
+
 /* TSE Stuff */
 #define ALTERA_TSE_CMD_TX_ENA_MSK		BIT(0)
 #define ALTERA_TSE_CMD_RX_ENA_MSK		BIT(1)
@@ -159,6 +218,7 @@ struct altera_tse_priv {
 	unsigned int tx_fifo_depth;
 	void *rx_desc;
 	void *tx_desc;
+	void *rx_resp;
 	unsigned char *rx_buf;
 	unsigned int phyaddr;
 	unsigned int interface;