diff options
| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2017-05-25 12:15:24 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2018-05-11 09:23:43 +0200 |
| commit | 9fdde6c4bbb6840dd175f0c29dfcc791fc0c1d2a (patch) | |
| tree | 7078dfef0965be1f3f6f2eb86c5d2da5d23ec575 /drivers/mtd | |
| parent | 9ca8388059de8f10e035fbdcaa418ec3caeb0599 (diff) | |
nand: zynq: Send address cycles as per onfi parameter page
Send address cycles as per value read from onfi parameter
page for Read and write commands instead of using a
hard coded value. This may vary for different parts and
hence use it from onfi parameter page value.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/nand/zynq_nand.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c index 4d0ea9e6b9d..e932a58bf60 100644 --- a/drivers/mtd/nand/zynq_nand.c +++ b/drivers/mtd/nand/zynq_nand.c @@ -84,6 +84,9 @@ #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */ #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */ +#define ZYNQ_NAND_ROW_ADDR_CYCL_MASK 0x0F +#define ZYNQ_NAND_COL_ADDR_CYCL_MASK 0xF0 + #define ZYNQ_NAND_MIO_NUM_NAND_8BIT 13 #define ZYNQ_NAND_MIO_NUM_NAND_16BIT 8 @@ -778,6 +781,7 @@ static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command, { struct nand_chip *chip = mtd->priv; const struct zynq_nand_command_format *curr_cmd = NULL; + u8 addr_cycles = 0; struct zynq_nand_info *xnand = (struct zynq_nand_info *)chip->priv; void *cmd_addr; unsigned long cmd_data = 0; @@ -828,8 +832,18 @@ static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command, else end_cmd = curr_cmd->end_cmd; + if (command == NAND_CMD_READ0 || + command == NAND_CMD_SEQIN) { + addr_cycles = chip->onfi_params.addr_cycles & + ZYNQ_NAND_ROW_ADDR_CYCL_MASK; + addr_cycles += ((chip->onfi_params.addr_cycles & + ZYNQ_NAND_COL_ADDR_CYCL_MASK) >> 4); + } else { + addr_cycles = curr_cmd->addr_cycles; + } + cmd_phase_addr = (unsigned long)xnand->nand_base | - (curr_cmd->addr_cycles << ADDR_CYCLES_SHIFT) | + (addr_cycles << ADDR_CYCLES_SHIFT) | (end_cmd_valid << END_CMD_VALID_SHIFT) | (COMMAND_PHASE) | (end_cmd << END_CMD_SHIFT) | |