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authorJagannadha Sutradharudu Teki <jaganna@xilinx.com>2013-12-26 13:54:57 +0530
committerJagannadha Sutradharudu Teki <jaganna@xilinx.com>2014-01-11 15:13:26 +0530
commitd08a1baf617a8b7f1959c6b24c1ee7590a0c06a5 (patch)
treecc3d76e62567f51f9051d3aabd224689a7bd17b8 /drivers/mtd/spi/sf_internal.h
parent6cba6fdf96f13a0533187b9c16608d9ca44add40 (diff)
sf: Set quad enable bit support
This patch provides support to set the quad enable bit on flash. quad enable bit needs to set before performing any quad IO operations on respective SPI flashes. Currently added set quad enable bit for winbond and spansion flash devices. stmicro flash doesn't require to set as qeb is volatile. remaining flash devices support will add in future patches. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Diffstat (limited to 'drivers/mtd/spi/sf_internal.h')
-rw-r--r--drivers/mtd/spi/sf_internal.h10
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index dcc9014e5f7..dca34f7a715 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -12,6 +12,11 @@
#define SPI_FLASH_16MB_BOUN 0x1000000
+/* CFI Manufacture ID's */
+#define SPI_FLASH_CFI_MFR_SPANSION 0x01
+#define SPI_FLASH_CFI_MFR_STMICRO 0x20
+#define SPI_FLASH_CFI_MFR_WINBOND 0xef
+
/* SECT flags */
#define SECT_4K (1 << 1)
#define SECT_32K (1 << 2)
@@ -52,6 +57,7 @@
/* Common status */
#define STATUS_WIP 0x01
+#define STATUS_QEB_WINSPAN (1 << 1)
#define STATUS_PEC 0x80
/* Flash timeout values */
@@ -93,8 +99,8 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
/* Program the status register */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
-/* Set quad enbale bit */
-int spi_flash_set_qeb(struct spi_flash *flash);
+/* Set quad enbale bit for winbond and spansion flashes */
+int spi_flash_set_qeb_winspan(struct spi_flash *flash);
/* Enable writing on the SPI flash */
static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)