diff options
| author | Simon Glass <sjg@chromium.org> | 2011-05-19 17:56:33 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2011-08-24 10:01:51 -0700 |
| commit | f22424f2c7b085a88eb6b750c6acca1e2d133e9c (patch) | |
| tree | 73b4d58fd2af0e64114f6b502a16cf6a33a02bd8 /drivers/mmc | |
| parent | a9177e1137f15505a0a5718e46167f43baede92b (diff) | |
tegra2: Add clock and PLL control functions
This adds functions for setting up clocks to peripherals, by selecting
a parent clock and specifying a rate.
BUG=chromium-os:13228
TEST=Build, boot on Seaboard
Change-Id: I957723b5f0ef64244c16f44ae7cbd79abf06427d
Reviewed-on: http://gerrit.chromium.org/gerrit/1290
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/tegra2_mmc.c | 37 |
1 files changed, 14 insertions, 23 deletions
diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c index 8b6f829e738..d69bbefd810 100644 --- a/drivers/mmc/tegra2_mmc.c +++ b/drivers/mmc/tegra2_mmc.c @@ -23,6 +23,7 @@ #include <mmc.h> #include <asm/io.h> #include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> #include "tegra2_mmc.h" /* support 4 mmc hosts */ @@ -277,8 +278,9 @@ static void mmc_change_clock(struct mmc_host *host, uint clock) int div, hw_div; unsigned short clk; unsigned long timeout; - unsigned int reg, hostbase; - struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + unsigned int hostbase; + enum periph_id mmc_id = PERIPH_ID_SDMMC1; + debug(" mmc_change_clock called\n"); /* Change Tegra2 SDMMCx clock divisor here */ @@ -305,27 +307,16 @@ static void mmc_change_clock(struct mmc_host *host, uint clock) hostbase = readl(&host->base); debug("mmc_change_clock: hostbase = %08X\n", hostbase); - if (hostbase == TEGRA2_SDMMC1_BASE) { - reg = readl(&clkrst->crc_clk_src_sdmmc1); - reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */ - reg |= hw_div; /* n-1 */ - writel(reg, &clkrst->crc_clk_src_sdmmc1); - } else if (hostbase == TEGRA2_SDMMC2_BASE) { - reg = readl(&clkrst->crc_clk_src_sdmmc2); - reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */ - reg |= hw_div; /* n-1 */ - writel(reg, &clkrst->crc_clk_src_sdmmc2); - } else if (hostbase == TEGRA2_SDMMC3_BASE) { - reg = readl(&clkrst->crc_clk_src_sdmmc3); - reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */ - reg |= hw_div; /* n-1 */ - writel(reg, &clkrst->crc_clk_src_sdmmc3); - } else { - reg = readl(&clkrst->crc_clk_src_sdmmc4); - reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */ - reg |= hw_div; /* n-1 */ - writel(reg, &clkrst->crc_clk_src_sdmmc4); - } + /* TODO: We need to record the PERIPH_ID, not the hostbase */ + if (hostbase == TEGRA2_SDMMC1_BASE) + mmc_id = PERIPH_ID_SDMMC1; + else if (hostbase == TEGRA2_SDMMC2_BASE) + mmc_id = PERIPH_ID_SDMMC2; + else if (hostbase == TEGRA2_SDMMC3_BASE) + mmc_id = PERIPH_ID_SDMMC3; + else if (hostbase == TEGRA2_SDMMC4_BASE) + mmc_id = PERIPH_ID_SDMMC4; + clock_ll_set_source_divisor(mmc_id, CLOCK_ID_PERIPH, hw_div); writew(0, &host->reg->clkcon); |