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author | Hai Pham <hai.pham.ud@renesas.com> | 2023-01-26 21:06:04 +0100 |
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committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2023-02-02 01:49:20 +0100 |
commit | c287c184aea435ef17ff5d11c3e06540dd2db0d7 (patch) | |
tree | 64c058ca72774f2245ade21dde16edbb27b9f9c7 /drivers/mmc/renesas-sdhi.c | |
parent | a1ec0bbc282ca02175f9b5efb41c1bc4a16a9e9c (diff) |
clk: renesas: Handle E3/D3 RPCSRC clock
The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car
E3, but uses a different pre-divider for the PLL0 parent. Add a new
macro to describe it, reusing the existing clock type for R-Car E3.
As both E3/D3 RPCSRC clock divider are different from the rest of R-Car
Gen3, keep the original implementation from Linux.
Based on Linux commit 40745482eec8 ("clk: renesas: r8a774c0: Add RPC
clocks") by Lad Prabhakar and 9d18f81b3535 ("clk: renesas: r8a77995: Add
RPC clocks") by Geert Uytterhoeven.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Add D3 tweaks
Diffstat (limited to 'drivers/mmc/renesas-sdhi.c')
0 files changed, 0 insertions, 0 deletions