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authorLaurentiu Tudor <laurentiu.tudor@nxp.com>2018-08-09 15:19:44 +0300
committerYork Sun <york.sun@nxp.com>2018-08-10 10:35:22 -0700
commit92d2e89c8c44a8f41d5f296e46c9cd6c9b34e4f8 (patch)
treec08fcfd662888906691e0e04466321c8e28c1f4d /drivers/misc
parent5bdfdb7d4fc23fdc458c0f51fe39f0b9c47a2744 (diff)
misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms
QMAN_BAR{E} register setup was disabled on ARM platforms, however the register does need to be set. Enable the code also on ARMs and fix the CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly enabled code works. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'drivers/misc')
-rw-r--r--drivers/misc/fsl_portals.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
index 7c22b8d209..22faf16751 100644
--- a/drivers/misc/fsl_portals.c
+++ b/drivers/misc/fsl_portals.c
@@ -24,7 +24,6 @@ void setup_qbman_portals(void)
CONFIG_SYS_BMAN_SWP_ISDR_REG;
void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
CONFIG_SYS_QMAN_SWP_ISDR_REG;
-#ifdef CONFIG_PPC
struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
@@ -32,7 +31,6 @@ void setup_qbman_portals(void)
out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
#endif
out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
-#endif
#ifdef CONFIG_FSL_CORENET
int i;