Merge tag 'xilinx-for-v2022.07-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.07-rc1 v2

xilinx:
- Allow booting bigger kernels till 100MB

zynqmp:
- DT updates (reset IDs)
- Remove unneeded low level uart initialization from psu_init*
- Enable PWM features
- Add support for 1EG device

serial_zynq:
- Change fifo behavior in DEBUG mode

zynq_sdhci:
- Fix BASECLK setting calculation

clk_zynqmp:
- Add support for showing video clock

gpio:
- Update slg driver to handle DT flags

net:
- Update ethernet_id code to support also DM_ETH_PHY
- Add support for DM_ETH_PHY in gem driver
- Enable dynamic mode for SGMII config in gem driver

pwm:
- Add driver for cadence PWM

versal:
- Add support for reserved memory

firmware:
- Handle PD enabling for SPL
- Add support for IOUSLCR SGMII configurations

include:
- Sync phy.h with Linux
- Update xilinx power domain dt binding headers

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpio/gpio_slg7xl45106.c b/drivers/gpio/gpio_slg7xl45106.c
index 2cbf7488ad6..4ad06c18b4b 100644
--- a/drivers/gpio/gpio_slg7xl45106.c
+++ b/drivers/gpio/gpio_slg7xl45106.c
@@ -11,6 +11,7 @@
 #include <asm/gpio.h>
 #include <dm.h>
 #include <i2c.h>
+#include <dt-bindings/gpio/gpio.h>
 #include <asm/arch/hardware.h>
 
 #define SLG7XL45106_REG		0xdb
@@ -26,6 +27,7 @@ static int slg7xl45106_i2c_gpo_xlate(struct udevice *dev,
 				     struct ofnode_phandle_args *args)
 {
 	desc->offset = (unsigned int)args->args[0];
+	desc->flags = (args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);
 
 	return 0;
 }