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authorSimon Glass <sjg@chromium.org>2020-12-03 16:55:18 -0700
committerSimon Glass <sjg@chromium.org>2020-12-13 16:51:08 -0700
commitcaa4daa2ae3dc0a3e516addea5772c9af76abcb0 (patch)
tree0abbc5b538894532f4db28d56e4645d3be230d27 /drivers/gpio/zynq_gpio.c
parent41575d8e4c334df148c4cdd7c40cc825dc0fcaa1 (diff)
dm: treewide: Rename 'platdata' variables to just 'plat'
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/gpio/zynq_gpio.c')
-rw-r--r--drivers/gpio/zynq_gpio.c58
1 files changed, 29 insertions, 29 deletions
diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
index 4ef2985e76..cfe35674b7 100644
--- a/drivers/gpio/zynq_gpio.c
+++ b/drivers/gpio/zynq_gpio.c
@@ -193,20 +193,20 @@ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
unsigned int *bank_pin_num,
struct udevice *dev)
{
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
u32 bank;
- for (bank = 0; bank < platdata->p_data->max_bank; bank++) {
- if (pin_num >= platdata->p_data->bank_min[bank] &&
- pin_num <= platdata->p_data->bank_max[bank]) {
+ for (bank = 0; bank < plat->p_data->max_bank; bank++) {
+ if (pin_num >= plat->p_data->bank_min[bank] &&
+ pin_num <= plat->p_data->bank_max[bank]) {
*bank_num = bank;
*bank_pin_num = pin_num -
- platdata->p_data->bank_min[bank];
+ plat->p_data->bank_min[bank];
return;
}
}
- if (bank >= platdata->p_data->max_bank) {
+ if (bank >= plat->p_data->max_bank) {
printf("Invalid bank and pin num\n");
*bank_num = 0;
*bank_pin_num = 0;
@@ -215,9 +215,9 @@ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
static int gpio_is_valid(unsigned gpio, struct udevice *dev)
{
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
- return gpio < platdata->p_data->ngpio;
+ return gpio < plat->p_data->ngpio;
}
static int check_gpio(unsigned gpio, struct udevice *dev)
@@ -233,14 +233,14 @@ static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
{
u32 data;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
- data = readl(platdata->base +
+ data = readl(plat->base +
ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
return (data >> bank_pin_num) & 1;
@@ -249,7 +249,7 @@ static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
{
unsigned int reg_offset, bank_num, bank_pin_num;
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
@@ -272,7 +272,7 @@ static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
- writel(value, platdata->base + reg_offset);
+ writel(value, plat->base + reg_offset);
return 0;
}
@@ -281,7 +281,7 @@ static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
@@ -293,9 +293,9 @@ static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
return -1;
/* clear the bit in direction mode reg to set the pin as input */
- reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg = readl(plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg &= ~BIT(bank_pin_num);
- writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ writel(reg, plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
return 0;
}
@@ -305,7 +305,7 @@ static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
@@ -313,14 +313,14 @@ static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
/* set the GPIO pin as output */
- reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg = readl(plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg |= BIT(bank_pin_num);
- writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ writel(reg, plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
/* configure the output enable reg for the pin */
- reg = readl(platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+ reg = readl(plat->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
reg |= BIT(bank_pin_num);
- writel(reg, platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+ writel(reg, plat->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
/* set the state of the pin */
zynq_gpio_set_value(dev, gpio, value);
@@ -331,7 +331,7 @@ static int zynq_gpio_get_function(struct udevice *dev, unsigned offset)
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
if (check_gpio(offset, dev) < 0)
return -1;
@@ -339,7 +339,7 @@ static int zynq_gpio_get_function(struct udevice *dev, unsigned offset)
zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);
/* set the GPIO pin as output */
- reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg = readl(plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg &= BIT(bank_pin_num);
if (reg)
return GPIOF_OUTPUT;
@@ -369,7 +369,7 @@ static const struct udevice_id zynq_gpio_ids[] = {
static int zynq_gpio_probe(struct udevice *dev)
{
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
const void *label_ptr;
@@ -382,19 +382,19 @@ static int zynq_gpio_probe(struct udevice *dev)
uc_priv->bank_name = dev->name;
}
- if (platdata->p_data)
- uc_priv->gpio_count = platdata->p_data->ngpio;
+ if (plat->p_data)
+ uc_priv->gpio_count = plat->p_data->ngpio;
return 0;
}
static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
{
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_platdata *plat = dev_get_platdata(dev);
- platdata->base = (phys_addr_t)dev_read_addr(dev);
+ plat->base = (phys_addr_t)dev_read_addr(dev);
- platdata->p_data =
+ plat->p_data =
(struct zynq_platform_data *)dev_get_driver_data(dev);
return 0;
@@ -407,5 +407,5 @@ U_BOOT_DRIVER(gpio_zynq) = {
.of_match = zynq_gpio_ids,
.ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
.probe = zynq_gpio_probe,
- .platdata_auto = sizeof(struct zynq_gpio_platdata),
+ .plat_auto = sizeof(struct zynq_gpio_platdata),
};