fpga: virtex2: cosmetic: Cleanup code style

Address Checkpatch warnings in virtex2 code prior to making other
changes. No functional change intended.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

1 files changed, 136 insertions, 134 deletions

diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index 02773d6a0e..b01a31f080 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -19,16 +19,16 @@
 #endif
 
 #ifdef	FPGA_DEBUG
-#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#define	PRINTF(fmt, args...)	printf(fmt, ##args)
 #else
-#define PRINTF(fmt,args...)
+#define PRINTF(fmt, args...)
 #endif
 
 /*
  * If the SelectMap interface can be overrun by the processor, define
- * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration
- * file and add board-specific support for checking BUSY status. By default,
- * assume that the SelectMap interface cannot be overrun.
+ * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board
+ * configuration file and add board-specific support for checking BUSY status.
+ * By default, assume that the SelectMap interface cannot be overrun.
  */
 #ifndef CONFIG_SYS_FPGA_CHECK_BUSY
 #undef CONFIG_SYS_FPGA_CHECK_BUSY
@@ -65,7 +65,7 @@
  * an XC2V1000, if anyone can ever get ahold of one.
  */
 #ifndef CONFIG_SYS_FPGA_WAIT_INIT
-#define CONFIG_SYS_FPGA_WAIT_INIT	CONFIG_SYS_HZ/2	/* 500 ms */
+#define CONFIG_SYS_FPGA_WAIT_INIT	CONFIG_SYS_HZ / 2	/* 500 ms */
 #endif
 
 /*
@@ -74,14 +74,14 @@
  * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
  */
 #ifndef CONFIG_SYS_FPGA_WAIT_BUSY
-#define CONFIG_SYS_FPGA_WAIT_BUSY	CONFIG_SYS_HZ/200	/* 5 ms*/
+#define CONFIG_SYS_FPGA_WAIT_BUSY	CONFIG_SYS_HZ / 200	/* 5 ms*/
 #endif
 
 /* Default timeout for waiting for FPGA to enter operational mode after
  * configuration data has been written.
  */
 #ifndef	CONFIG_SYS_FPGA_WAIT_CONFIG
-#define CONFIG_SYS_FPGA_WAIT_CONFIG	CONFIG_SYS_HZ/5	/* 200 ms */
+#define CONFIG_SYS_FPGA_WAIT_CONFIG	CONFIG_SYS_HZ / 5	/* 200 ms */
 #endif
 
 static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
@@ -97,18 +97,18 @@ static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
 
 	switch (desc->iface) {
 	case slave_serial:
-		PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
+		PRINTF("%s: Launching Slave Serial Load\n", __func__);
 		ret_val = virtex2_ss_load(desc, buf, bsize);
 		break;
 
 	case slave_selectmap:
-		PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
+		PRINTF("%s: Launching Slave Parallel Load\n", __func__);
 		ret_val = virtex2_ssm_load(desc, buf, bsize);
 		break;
 
 	default:
-		printf ("%s: Unsupported interface type, %d\n",
-				__FUNCTION__, desc->iface);
+		printf("%s: Unsupported interface type, %d\n",
+		       __func__, desc->iface);
 	}
 	return ret_val;
 }
@@ -119,18 +119,18 @@ static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 
 	switch (desc->iface) {
 	case slave_serial:
-		PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
+		PRINTF("%s: Launching Slave Serial Dump\n", __func__);
 		ret_val = virtex2_ss_dump(desc, buf, bsize);
 		break;
 
 	case slave_parallel:
-		PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
+		PRINTF("%s: Launching Slave Parallel Dump\n", __func__);
 		ret_val = virtex2_ssm_dump(desc, buf, bsize);
 		break;
 
 	default:
-		printf ("%s: Unsupported interface type, %d\n",
-				__FUNCTION__, desc->iface);
+		printf("%s: Unsupported interface type, %d\n",
+		       __func__, desc->iface);
 	}
 	return ret_val;
 }
@@ -159,135 +159,135 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 	int ret_val = FPGA_FAIL;
 	xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
 
-	PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
-			__FUNCTION__, __LINE__, fn);
+	PRINTF("%s:%d: Start with interface functions @ 0x%p\n",
+	       __func__, __LINE__, fn);
 
 	if (fn) {
 		size_t bytecount = 0;
-		unsigned char *data = (unsigned char *) buf;
+		unsigned char *data = (unsigned char *)buf;
 		int cookie = desc->cookie;
 		unsigned long ts;
 
 		/* Gotta split this one up (so the stack won't blow??) */
-		PRINTF ("%s:%d: Function Table:\n"
-				"  base   0x%p\n"
-				"  struct 0x%p\n"
-				"  pre    0x%p\n"
-				"  prog   0x%p\n"
-				"  init   0x%p\n"
-				"  error  0x%p\n",
-				__FUNCTION__, __LINE__,
-				&fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
-		PRINTF ("  clock  0x%p\n"
-				"  cs     0x%p\n"
-				"  write  0x%p\n"
-				"  rdata  0x%p\n"
-				"  wdata  0x%p\n"
-				"  busy   0x%p\n"
-				"  abort  0x%p\n"
-				"  post   0x%p\n\n",
-				fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
-				fn->busy, fn->abort, fn->post);
+		PRINTF("%s:%d: Function Table:\n"
+		       "  base   0x%p\n"
+		       "  struct 0x%p\n"
+		       "  pre    0x%p\n"
+		       "  prog   0x%p\n"
+		       "  init   0x%p\n"
+		       "  error  0x%p\n",
+		       __func__, __LINE__,
+		       &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
+		PRINTF("  clock  0x%p\n"
+		       "  cs     0x%p\n"
+		       "  write  0x%p\n"
+		       "  rdata  0x%p\n"
+		       "  wdata  0x%p\n"
+		       "  busy   0x%p\n"
+		       "  abort  0x%p\n"
+		       "  post   0x%p\n\n",
+		       fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
+		       fn->busy, fn->abort, fn->post);
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-		printf ("Initializing FPGA Device %d...\n", cookie);
+		printf("Initializing FPGA Device %d...\n", cookie);
 #endif
 		/*
 		 * Run the pre configuration function if there is one.
 		 */
-		if (*fn->pre) {
-			(*fn->pre) (cookie);
-		}
+		if (*fn->pre)
+			(*fn->pre)(cookie);
 
 		/*
 		 * Assert the program line.  The minimum pulse width for
-		 * Virtex II devices is 300 nS (Tprogram parameter in datasheet).
-		 * There is no maximum value for the pulse width.  Check to make
-		 * sure that INIT_B goes low after assertion of PROG_B
+		 * Virtex II devices is 300 nS (Tprogram parameter in
+		 * datasheet). There is no maximum value for the pulse width.
+		 * Check to make sure that INIT_B goes low after assertion of
+		 * PROG_B
 		 */
-		(*fn->pgm) (true, true, cookie);
-		udelay (10);
-		ts = get_timer (0);
+		(*fn->pgm)(true, true, cookie);
+		udelay(10);
+		ts = get_timer(0);
 		do {
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
-				printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
-						" to assert.\n", __FUNCTION__, __LINE__,
-						CONFIG_SYS_FPGA_WAIT_INIT);
-				(*fn->abort) (cookie);
+			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+				printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
+				       __func__, __LINE__,
+				       CONFIG_SYS_FPGA_WAIT_INIT);
+				(*fn->abort)(cookie);
 				return FPGA_FAIL;
 			}
-		} while (!(*fn->init) (cookie));
+		} while (!(*fn->init)(cookie));
 
-		(*fn->pgm) (false, true, cookie);
-		CONFIG_FPGA_DELAY ();
-		(*fn->clk) (true, true, cookie);
+		(*fn->pgm)(false, true, cookie);
+		CONFIG_FPGA_DELAY();
+		(*fn->clk)(true, true, cookie);
 
 		/*
 		 * Start a timer and wait for INIT_B to go high
 		 */
-		ts = get_timer (0);
+		ts = get_timer(0);
 		do {
-			CONFIG_FPGA_DELAY ();
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
-				printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
-						" to deassert.\n", __FUNCTION__, __LINE__,
-						CONFIG_SYS_FPGA_WAIT_INIT);
-				(*fn->abort) (cookie);
+			CONFIG_FPGA_DELAY();
+			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+				printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
+				       __func__, __LINE__,
+				       CONFIG_SYS_FPGA_WAIT_INIT);
+				(*fn->abort)(cookie);
 				return FPGA_FAIL;
 			}
-		} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
+		} while ((*fn->init)(cookie) && (*fn->busy)(cookie));
 
-		(*fn->wr) (true, true, cookie);
-		(*fn->cs) (true, true, cookie);
+		(*fn->wr)(true, true, cookie);
+		(*fn->cs)(true, true, cookie);
 
-		udelay (10000);
+		mdelay(10);
 
 		/*
 		 * Load the data byte by byte
 		 */
 		while (bytecount < bsize) {
 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
-			if (ctrlc ()) {
-				(*fn->abort) (cookie);
+			if (ctrlc()) {
+				(*fn->abort)(cookie);
 				return FPGA_FAIL;
 			}
 #endif
 
-			if ((*fn->done) (cookie) == FPGA_SUCCESS) {
-			    PRINTF ("%s:%d:done went active early, bytecount = %d\n",
-				    __FUNCTION__, __LINE__, bytecount);
-			    break;
+			if ((*fn->done)(cookie) == FPGA_SUCCESS) {
+				PRINTF("%s:%d:done went active early, bytecount = %d\n",
+				       __func__, __LINE__, bytecount);
+				break;
 			}
 
 #ifdef CONFIG_SYS_FPGA_CHECK_ERROR
-			if ((*fn->init) (cookie)) {
-				printf ("\n%s:%d:  ** Error: INIT asserted during"
-						" configuration\n", __FUNCTION__, __LINE__);
-				printf ("%d = buffer offset, %d = buffer size\n",
-					bytecount, bsize);
-				(*fn->abort) (cookie);
+			if ((*fn->init)(cookie)) {
+				printf("\n%s:%d:  ** Error: INIT asserted during configuration\n",
+				       __func__, __LINE__);
+				printf("%d = buffer offset, %d = buffer size\n",
+				       bytecount, bsize);
+				(*fn->abort)(cookie);
 				return FPGA_FAIL;
 			}
 #endif
 
-			(*fn->wdata) (data[bytecount++], true, cookie);
-			CONFIG_FPGA_DELAY ();
+			(*fn->wdata)(data[bytecount++], true, cookie);
+			CONFIG_FPGA_DELAY();
 
 			/*
 			 * Cycle the clock pin
 			 */
-			(*fn->clk) (false, true, cookie);
-			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (true, true, cookie);
+			(*fn->clk)(false, true, cookie);
+			CONFIG_FPGA_DELAY();
+			(*fn->clk)(true, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
-			ts = get_timer (0);
-			while ((*fn->busy) (cookie)) {
-				if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
-					printf ("%s:%d: ** Timeout after %d ticks waiting for"
-							" BUSY to deassert\n",
-							__FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_BUSY);
-					(*fn->abort) (cookie);
+			ts = get_timer(0);
+			while ((*fn->busy)(cookie)) {
+				if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
+					printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
+					       __func__, __LINE__,
+					       CONFIG_SYS_FPGA_WAIT_BUSY);
+					(*fn->abort)(cookie);
 					return FPGA_FAIL;
 				}
 			}
@@ -295,33 +295,35 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
-				putc ('.');
+				putc('.');
 #endif
 		}
 
 		/*
-		 * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
+		 * Finished writing the data; deassert FPGA CS_B and WRITE_B
+		 * signals.
 		 */
-		CONFIG_FPGA_DELAY ();
-		(*fn->cs) (false, true, cookie);
-		(*fn->wr) (false, true, cookie);
+		CONFIG_FPGA_DELAY();
+		(*fn->cs)(false, true, cookie);
+		(*fn->wr)(false, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-		putc ('\n');
+		putc('\n');
 #endif
 
 		/*
-		 * Check for successful configuration.  FPGA INIT_B and DONE should
-		 * both be high upon successful configuration.
+		 * Check for successful configuration.  FPGA INIT_B and DONE
+		 * should both be high upon successful configuration.
 		 */
-		ts = get_timer (0);
+		ts = get_timer(0);
 		ret_val = FPGA_SUCCESS;
-		while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) {
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
-				printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to"
-						"assert and INIT to deassert\n",
-						__FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
-				(*fn->abort) (cookie);
+		while (((*fn->done)(cookie) == FPGA_FAIL) ||
+		       (*fn->init)(cookie)) {
+			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
+				printf("%s:%d: ** Timeout after %d ticks waiting for DONE toassert and INIT to deassert\n",
+				       __func__, __LINE__,
+				       CONFIG_SYS_FPGA_WAIT_CONFIG);
+				(*fn->abort)(cookie);
 				ret_val = FPGA_FAIL;
 				break;
 			}
@@ -329,23 +331,23 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 
 		if (ret_val == FPGA_SUCCESS) {
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-			printf ("Initialization of FPGA device %d complete\n", cookie);
+			printf("Initialization of FPGA device %d complete\n",
+			       cookie);
 #endif
 			/*
 			 * Run the post configuration function if there is one.
 			 */
-			if (*fn->post) {
-				(*fn->post) (cookie);
-			}
+			if (*fn->post)
+				(*fn->post)(cookie);
 		} else {
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-			printf ("** Initialization of FPGA device %d FAILED\n",
-					cookie);
+			printf("** Initialization of FPGA device %d FAILED\n",
+			       cookie);
 #endif
 		}
 	} else {
-		printf ("%s:%d: NULL Interface function table!\n",
-				__FUNCTION__, __LINE__);
+		printf("%s:%d: NULL Interface function table!\n",
+		       __func__, __LINE__);
 	}
 	return ret_val;
 }
@@ -359,61 +361,61 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 	xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
 
 	if (fn) {
-		unsigned char *data = (unsigned char *) buf;
+		unsigned char *data = (unsigned char *)buf;
 		size_t bytecount = 0;
 		int cookie = desc->cookie;
 
-		printf ("Starting Dump of FPGA Device %d...\n", cookie);
+		printf("Starting Dump of FPGA Device %d...\n", cookie);
 
-		(*fn->cs) (true, true, cookie);
-		(*fn->clk) (true, true, cookie);
+		(*fn->cs)(true, true, cookie);
+		(*fn->clk)(true, true, cookie);
 
 		while (bytecount < bsize) {
 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
-			if (ctrlc ()) {
-				(*fn->abort) (cookie);
+			if (ctrlc()) {
+				(*fn->abort)(cookie);
 				return FPGA_FAIL;
 			}
 #endif
 			/*
 			 * Cycle the clock and read the data
 			 */
-			(*fn->clk) (false, true, cookie);
-			(*fn->clk) (true, true, cookie);
-			(*fn->rdata) (&(data[bytecount++]), cookie);
+			(*fn->clk)(false, true, cookie);
+			(*fn->clk)(true, true, cookie);
+			(*fn->rdata)(&data[bytecount++], cookie);
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
-				putc ('.');
+				putc('.');
 #endif
 		}
 
 		/*
 		 * Deassert CS_B and cycle the clock to deselect the device.
 		 */
-		(*fn->cs) (false, false, cookie);
-		(*fn->clk) (false, true, cookie);
-		(*fn->clk) (true, true, cookie);
+		(*fn->cs)(false, false, cookie);
+		(*fn->clk)(false, true, cookie);
+		(*fn->clk)(true, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-		putc ('\n');
+		putc('\n');
 #endif
-		puts ("Done.\n");
+		puts("Done.\n");
 	} else {
-		printf ("%s:%d: NULL Interface function table!\n",
-				__FUNCTION__, __LINE__);
+		printf("%s:%d: NULL Interface function table!\n",
+		       __func__, __LINE__);
 	}
 	return ret_val;
 }
 
 static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
-	printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
+	printf("%s: Slave Serial Loading is unsupported\n", __func__);
 	return FPGA_FAIL;
 }
 
 static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
-	printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
+	printf("%s: Slave Serial Dumping is unsupported\n", __func__);
 	return FPGA_FAIL;
 }