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authorMarek Vasut <marex@denx.de>2015-07-27 22:34:54 +0200
committerMarek Vasut <marex@denx.de>2015-08-08 14:14:04 +0200
commitbfa89d2ba8f0a278df6de584dcfbd33814753e33 (patch)
treeea240198443d00cd6814d24a77e2aa7d6ddbf680 /drivers/fpga
parentae27120c31d58b8bb694d9155bcffdcfae8552a6 (diff)
arm: socfpga: Fix FPGA bitstream programming routine
In case the FPGA bitstream is aligned to 4 bytes, skip the part of the assembler which handles unaligned bitstream. Otherwise, that part will loop indefinitelly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'drivers/fpga')
-rw-r--r--drivers/fpga/socfpga.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index 63b3566e3ed..4448250f5c6 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -160,10 +160,13 @@ static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
" sub %1, #32\n"
" subs %2, #1\n"
" bne 1b\n"
+ " cmp %3, #0\n"
+ " beq 3f\n"
"2: ldr %2, [%0], #4\n"
" str %2, [%1]\n"
" subs %3, #1\n"
" bne 2b\n"
+ "3: nop\n"
: "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
}