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| author | T Karthik Reddy <t.karthik.reddy@xilinx.com> | 2020-05-14 07:49:36 -0600 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2020-06-24 13:11:08 +0200 |
| commit | 33d3f8e57754f9b498fa7c14408f2bc20be43900 (patch) | |
| tree | 1ec95dc0d8eaf878a5f4307ad48f82fa7f2e8662 /drivers/fpga/versalpl.c | |
| parent | f44bd3bcfd91cd7b1be709c9cfb0824e6a71b9b0 (diff) | |
arm64: xilinx: Print fpga error value in hex
Fpga returns error value when fails, error status should be
printed in hex format.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/fpga/versalpl.c')
| -rw-r--r-- | drivers/fpga/versalpl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index b96519e1a4..8e2ef4f0da 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -45,7 +45,7 @@ static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize, ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, buf_hi, 0, ret_payload); if (ret) - puts("PL FPGA LOAD fail\n"); + printf("PL FPGA LOAD failed with err: 0x%08x\n", ret); return ret; } |