ppc: Remove sbc8641d board

This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove it.  This is also the last
of the ARCH_MPC8641/MPC8610 platforms, so remove that support as well.

Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

3 files changed, 2 insertions, 95 deletions

diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 890e62190b..e6a51f5609 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -2,8 +2,8 @@ config SYS_FSL_DDR
 	bool
 	help
 	  Select Freescale General DDR driver, shared between most Freescale
-	  PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
-	  based Layerscape SoCs (such as ls2080a).
+	  PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
+	  Layerscape SoCs (such as ls2080a).
 
 config SYS_FSL_MMDC
 	bool
@@ -41,7 +41,6 @@ config SYS_NUM_DDR_CTLRS
 			ARCH_T4240
 	default 2 if	ARCH_B4860	|| \
 			ARCH_BSC9132	|| \
-			ARCH_MPC8641	|| \
 			ARCH_P4080	|| \
 			ARCH_P5040	|| \
 			ARCH_LX2160A	|| \
@@ -79,12 +78,6 @@ config SYS_FSL_DDRC_GEN2
 	help
 	  Enable Freescale DDR2 controller.
 
-config SYS_FSL_DDRC_86XX_GEN2
-	bool
-	depends on MPC86xx
-	help
-	  Enable Freescale DDR2 controller for MPC86xx SoCs.
-
 config SYS_FSL_DDRC_GEN3
 	bool
 	depends on PPC
@@ -136,7 +129,6 @@ config SYS_FSL_DDR2
 	bool "Freescale DDR2 controller"
 	depends on SYS_FSL_HAS_DDR2
 	select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
-	select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx
 
 config SYS_FSL_DDR1
 	bool "Freescale DDR1 controller"
diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
index c675f44ab0..8081d0cd82 100644
--- a/drivers/ddr/fsl/Makefile
+++ b/drivers/ddr/fsl/Makefile
@@ -28,7 +28,6 @@ obj-$(CONFIG_FSL_DDR_INTERACTIVE)	+= interactive.o
 obj-$(CONFIG_SYS_FSL_DDRC_GEN1)	+= mpc85xx_ddr_gen1.o
 obj-$(CONFIG_SYS_FSL_DDRC_GEN2)	+= mpc85xx_ddr_gen2.o
 obj-$(CONFIG_SYS_FSL_DDRC_GEN3)	+= mpc85xx_ddr_gen3.o
-obj-$(CONFIG_SYS_FSL_DDRC_86XX_GEN2)	+= mpc86xx_ddr.o
 obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3)	+= arm_ddr_gen3.o
 obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
 obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
diff --git a/drivers/ddr/fsl/mpc86xx_ddr.c b/drivers/ddr/fsl/mpc86xx_ddr.c
deleted file mode 100644
index 43ed1ba432..0000000000
--- a/drivers/ddr/fsl/mpc86xx_ddr.c
+++ /dev/null
@@ -1,84 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <fsl_ddr_sdram.h>
-#include <linux/delay.h>
-
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
-#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
-#endif
-
-void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-			     unsigned int ctrl_num, int step)
-{
-	unsigned int i;
-	struct ccsr_ddr __iomem *ddr;
-
-	switch (ctrl_num) {
-	case 0:
-		ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
-		break;
-	case 1:
-		ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
-		break;
-	default:
-		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
-		return;
-	}
-
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (i == 0) {
-			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs0_config, regs->cs[i].config);
-
-		} else if (i == 1) {
-			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs1_config, regs->cs[i].config);
-
-		} else if (i == 2) {
-			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs2_config, regs->cs[i].config);
-
-		} else if (i == 3) {
-			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs3_config, regs->cs[i].config);
-		}
-	}
-
-	out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
-	out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
-	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
-	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
-	out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
-	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
-	out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
-	out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
-	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
-	out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
-	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-	out_be32(&ddr->init_addr, regs->ddr_init_addr);
-	out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
-
-	debug("before go\n");
-
-	/*
-	 * 200 painful micro-seconds must elapse between
-	 * the DDR clock setup and the DDR config enable.
-	 */
-	udelay(200);
-	asm volatile("sync;isync");
-
-	out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
-
-	/*
-	 * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
-	 */
-	while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
-		udelay(10000);		/* throttle polling rate */
-	}
-}