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authorYork Sun <yorksun@freescale.com>2014-06-23 15:36:44 -0700
committerYork Sun <yorksun@freescale.com>2014-07-22 16:25:54 -0700
commit8340e7ac86ad3c59956e8f0bd627b741e5209439 (patch)
tree0460d0395f63b1cee89ae8dfe5479ace02bb5c50 /drivers/ddr
parent6666017f44e39ec0385e3c7736b8c9af46cf4f08 (diff)
driver/ddr: Fix DDR4 driver for ARM
Previously the driver was only tested on Power SoCs. Different barrier instructions are needed for ARM SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr')
-rw-r--r--drivers/ddr/fsl/fsl_ddr_gen4.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 7cd878aeecb..bfc76b34857 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -8,6 +8,7 @@
#include <asm/io.h>
#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
+#include <fsl_immap.h>
#include <fsl_ddr.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
@@ -183,12 +184,14 @@ step2:
* we choose the max, that is 500 us for all of case.
*/
udelay(500);
- asm volatile("sync;isync");
+ mb();
+ isb();
/* Let the controller go */
temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
- asm volatile("sync;isync");
+ mb();
+ isb();
total_gb_size_per_controller = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {