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authorMarek Vasut <marex@denx.de>2015-08-01 20:12:31 +0200
committerMarek Vasut <marex@denx.de>2015-08-08 14:14:26 +0200
commitad2ba5d60774172c0651d6ed5e2e889251ed0d32 (patch)
treeba09e4170bbacc98996078dbc576cce666f69ebe /drivers/ddr
parenta5ba9296710522d1916795a81074cf9d6659d7a0 (diff)
ddr: altera: sdram: Clean up set_sdr_mp_pacing()
Get rid of the constant clrsetbits_le32(), instead prepare the whole content of the register once and write it at the end of the function. Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'drivers/ddr')
-rw-r--r--drivers/ddr/altera/sdram.c37
1 files changed, 16 insertions, 21 deletions
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
index f3248055d14..e41815b3a12 100644
--- a/drivers/ddr/altera/sdram.c
+++ b/drivers/ddr/altera/sdram.c
@@ -441,31 +441,26 @@ static void set_sdr_mp_weight(void)
static void set_sdr_mp_pacing(void)
{
- debug("Configuring MPPACING_MPPACING_0\n");
- clrsetbits_le32(&sdr_ctrl->mp_pacing0,
- SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
+ const u32 mp_pacing0 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB);
-
- clrsetbits_le32(&sdr_ctrl->mp_pacing1,
- SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
- SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB);
-
- clrsetbits_le32(&sdr_ctrl->mp_pacing1,
- SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
+ const u32 mp_pacing1 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB);
-
- clrsetbits_le32(&sdr_ctrl->mp_pacing2,
- SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
+ const u32 mp_pacing2 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB);
-
- clrsetbits_le32(&sdr_ctrl->mp_pacing3,
- SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
+ const u32 mp_pacing3 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB);
+
+ debug("Configuring MPPACING_MPPACING_0\n");
+ writel(mp_pacing0, &sdr_ctrl->mp_pacing0);
+ writel(mp_pacing1, &sdr_ctrl->mp_pacing1);
+ writel(mp_pacing2, &sdr_ctrl->mp_pacing2);
+ writel(mp_pacing3, &sdr_ctrl->mp_pacing3);
}
static void set_sdr_mp_threshold(void)