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authorSaksham Jain <saksham.jain@nxp.com>2016-03-23 16:24:41 +0530
committerYork Sun <york.sun@nxp.com>2016-03-29 08:46:22 -0700
commit69b6a796f7a7cf2a7946e07e32346bf5595829d5 (patch)
tree048c8140e739a02d372fed20ee975691690864c1 /drivers/crypto
parent4a97a0c91d25763d7c3af5530c5e89f53fee7643 (diff)
crypto/fsl: Correct 64-bit write when MMU disabled
When MMU is disabled, 64-bit write must be aligned at 64-bit boundary. Becaue the memory location is not guaranteed to be 64-bit aligned, the 64-bit write needs to be split into two 32-bit writes to avoid the alignment exception. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'drivers/crypto')
-rw-r--r--drivers/crypto/fsl/desc_constr.h7
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index 4ea93b03a2..7dad753981 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -112,10 +112,9 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
#ifdef CONFIG_PHYS_64BIT
/* The Position of low and high part of 64 bit address
* will depend on the endianness of CAAM Block */
- union ptr_addr_t ptr_addr;
- ptr_addr.m_halfs.high = (u32)(ptr >> 32);
- ptr_addr.m_halfs.low = (u32)ptr;
- *offset = ptr_addr.m_whole;
+ union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset;
+ ptr_addr->m_halfs.high = (u32)(ptr >> 32);
+ ptr_addr->m_halfs.low = (u32)ptr;
#else
*offset = ptr;
#endif